연속 분할 방식 바이너리 옵션

미국 특허 72 발명자 Charles V Freiman Los Altos Chung Chian 왕 스탠포드, 캘리포니아 21 Appl No. 701,267 22 1968 년 1 월 29 일 출원 45 1977 년 7 월 6 일 73 양수인 International Business Machines Corporation Armonk, N Y. 54 DIVISION 시스템 및 방법 9 가지 청구 범위, 2 가지 도면, 52 235 164, 235 156 51 Int Cl 606i 7 39, G06f 7 38 50 연구 분야 235 164, 156. 561 참고 문헌 미국 특허 3,023,961 3 1962 Stafford 235 164 3,223,831 12 1965 Holleran 235 164 3,234,367 2 1966 Ottaway et a1 235 164 X 3,319,057 5 1967 Githens etal 235 164 3,378,677 4 1968 Waldecker 외 235 164 기타 참조 IBM 기술 공개 게시판, High Speed ​​Division Algorithum, DN Senzig, Vol 10 No 5, 1967 년 10 월 1 차 심사관 - 말콤 A 모리슨 조감독 - James Fv Gottman Attorney 변호사 Fraser 및 Bogucki 요약 테이블 룩업 및 반복 기법의 합성을 이용하는 디지털 분할을위한 시스템 및 방법 제수에 대해 곱해질 때, 1에 가깝게 미리 결정된 범위에서 새로운 제수를 제공하는 팩터 M을 생성하는 저장된 논리 테이블이 사용된다 그 다음에 제수와 배당은 인수 M으로 곱해진다. 새로운 제수의 최대 차이를 결정하는 표 검색의 용량 새로운 약수와 단위의 차이에 따라, 선택된 수의 새로운 부분 몫 지수가 새로 생성 된 부분 나머지의 선택된 자릿수로부터 직접 결정된다. 연속적인 그룹에서 몫 숫자를 생성함으로써, 단지 몇 번의 반복 하나의 긴 숫자를 다른 숫자로 나눌 필요가있다. 연속적인 분할 단계는 단지 새로운 부분 곱의 생성을 필요로하고, 이전의 부분 나머지와의 부분 곱의 차이를 유도한다. 새로운 제수의 중요한 부분을 이들 기술을 이용하는 고속의 고용량 이진 디지털 제산 시스템은 캐리 전파 지연을 도입하지 않고 캐리 및 합계 양을 이용하도록 캐리 세이브 가산기 회로를 이용하도록 구성되고, 그렇지 않으면 최소화된다 작동 사이클 시간. nmson mvmm fl LREHSIER 불신자 DIVISDI mvmnw l6 DlVlSlJll mm lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll이 (가) mm cmcuns aurm to cam-sue REIAIIDER amnion ADDER cm 일 ms ms nmsm 기록까지 채우기 J 10 몸무게가 늘어날 때까지 몸무게가 늘어남 W014i 수술 중 통증이 있음 38 tuonsln mm mm ouonw 1 PATENTEUJUL BIRD 3,591,787.SHEET 1 DE 2 l0 2 FIG -1 분배기 레지스터 등록기 7 새로운 분배기 - 분배기 분배기 분배기 회로 멀티플렉서 회로도 표제어 - 서브 우퍼 회람구 회로도 계산식 REDIET R NEW SMALL 20 D v soR REw DIVIDEND m ZZ 부분 곱 42 REGISTER E RMULTIPLIER I 40m DEERE ADDER BUFFER 24 개월차 26 28 28 일주일에 한 번 기억해보십시오. 기억해 두십시오. 기억을 되찾아주세요. 태양 나무 수첩. 등록기. 기록 보관함. 부양자. 부양비. swncmuc f3 수련자. 첫 번째 두 번째 수령인. 등록자 등록 부. 찰스 본 발명은 디지털 데이터 처리 시스템에 관한 것으로서, 더 상세하게는 디지털 분할 시스템 및 방법에 관한 것이다 .2 또한, 본 발명은 디지털 데이터 처리 시스템에 관한 것으로, 특히 디지털 분할 시스템 및 방법에 관한 것이다. 분할은 일반적으로 특히 길고 성가신 산술 연산이기 때문에 많은 상이한 분할 기술이 디지털 데이터 프로세서에 대해 공식화되었다. 분할 연산을 단순화하고 가속화하는 첫 번째 시도 중 하나는 제수의 역수 생성에 기초하고, 그 후 직선적 인 곱셈을 사용할 수있다. 그러나 상호가 발견 될 값에 따라, 시스템의 단어 길이 또는 형식이 필요한 정확도로 역수를 개발하기에 충분하지 않을 수있다. 따라서 대체적인 분할 방법이 일반적으로 이용 가능해야한다. 모든 사건 결과적으로이 접근법의 단점은 제한적입니다. 그것의 사용 범위. 두 가지 주요 접근 방식은 구분 작업을 용이하게하기 위해 시도되었습니다. 하나의 기술은 길이 구분과 대략적으로 비슷하며 일반적으로 비 복원 구분으로 불립니다. 이 분할 기술에서 몫 자리수와 제수의 곱은 첫 번째입니다 배장과 비교하여, 적절한 지수가 선택된 경우, 곱셈의 곱을 나머지에서 뺀 다음 새로운 나머지를 형성합니다. 새로운 지수를 선택적으로 연속적으로 선택합니다. 각 지수는 약수에 곱 해지고 부분 곱을 뺍니다 반면에 최종 지수에 도달 할 때까지 점진적으로 더 작은 나머지를 제공합니다. 반면에 잔여분 법으로 일반적으로 알려져있는 것에서는 지수 디지타이저의 반복적 인 전개가 사용되지 않지만 대신에 분자에 대한 곱셈에 대해 일반적인 곱셈 계수가 선택됩니다 와 분모를 사용하여 새로운 분모가 단일성에 접근하도록합니다. 이 방법에서, 곱셈 계수는 이전 반복에 대한 테이블 룩업 및 후속 반복에 대한 상대적으로 간단한 디코딩 룰을 이용하여 이전의 분모로부터 결정된다. 상기 기술 모두는 증가 된 속도 및 능력이 요구되는 조건이 발생할 때 특정 내재적 제한을 갖는다 미래의 초 고용량, 고속 디지털 컴퓨팅 시스템의 경우, 예를 들어 분할 명령의 신속한 실행이 중요한 요구 사항입니다. 결과적으로 성능이 향상되면 많은 양의 회로 사용이 필요하며 허용 될 수 있습니다. 크기 , 속도 및 용량이 증가 될 때마다 비 반복 분절 기술에서 과도한 문제가 발생합니다. 각 연속 반복에서 포괄해야 할 선택의 폭이 매우 크기 때문에 나머지 분업 기술에는 풀 (full) 곱셈과 뺄셈 더 중요하게는, 특정 조건 하에서 이들 기술은 모호한 값을 발생시키고 추가 동작 시퀀스 및 그에 따른 추가 시간을 요구하여 나머지의 부호를 확인한다. 본 발명에 따른 개선 된 고속, 고용량 분할 시스템 본 발명은 테이블 룩업 및 비 복원 분할 기술의 조합을 사용하며, 제수의 값은 1에 근사하는 미리 결정된 범위 내의 값을 갖는 새로운 제수를 설정하는 승수 인자 M을 생성하는데 이용된다. 새로운 제수의 근사 정도는 테이블 룩업 시스템의 용량에 의존하며, 필요한 후속 반복의 수를 결정한다. 배당은 M을 곱하여 초기 전체 잉여를 제공한다. 시스템의 특성은 주어진 수의 상위 자리수가 초기 전체 나머지 및 후속 부분 나머지는 부분 ial quotient values ​​부분 곱과 새로운 나누기의 곱셈에 의해 유도 된 부분 곱을 나머지 값에서 뺀 다음 나머지를 제공합니다. 연속적인 반복은 몫이 필요한 정밀도로 개발 될 때까지 해당 자릿수 그룹에 의해 나머지를 연속적으로 줄입니다. 부분 몫은 개별적으로 축적되어 궁극적으로 결합되거나 누적 적으로 결합 될 수있다. 본 발명에 따른 특정 구성은 디지털 데이터 처리 시스템에 대한 동작 속도에서 실질적인 이점을 제공한다. 새로운 작은 약수 값은 새로운 제수 및 단일성을 가지며 사전 결정된 수의 상위 자릿수가 0 인이 사전 결정된 수는 특히 워드 길이로 배열 된 수의 나눗셈에 필요한 반복 횟수를 제어한다. 또한 본 발명에 따르면 특히 고속 처리 배열이 유효 몫 그룹 및 부분 나머지 부분은 carry-save 형식으로 유지되며 부분 제품과 함께 carry-save adder 시스템에 적용됩니다. 부분 곱은 carry 곱셈과 덧셈 값을 디코딩하여 carry propagation delay없이 생성되어 곱셈을 직접 제어합니다. 잉여 캐리 및 합계 값에 응답하여 이진 곱셈기가 이진 곱셈기의 연속적인 디지털 장소들에 응답하여 시프트를 가지거나 가지지 않고 추가 될지 여부를 결정함으로써 곱셈을 제어한다. 본 발명에 따른 시스템들은 이진, 십진수 및 기타 수 시스템 본 발명에 따른 방법은 연속적인 지수 디지트에 대한 복잡한 선택 절차를 필요로하지 않고 비교적 단순화 된 분할 기술을 제공한다. 주어진 애플리케이션에 대한 최적의 크기 및 속도 관계의 선택은 공통 곱셈 인자 M의 선택을 제어함으로써 촉진 될 수있다. 처음 전술 한 목적 및 다른 목적, 특징 및 이점은 첨부 된 도면에 의해 예시 된 바와 같은 본 발명의 바람직한 실시 예에 대한 다음의 더욱 상세한 설명으로부터 명백해질 것이다. 도 1은 본 발명의 일 실시 예에 따른 블록 다이어그램 도 2는 본 발명에 따른 시스템들에 사용 된 몫 디코더 회로의 예시적인 부분의 블록도이다. 도 1의 시스템 도 1에 도시 된 다수의 주요 기능 유닛이 또한 다른 시간에 다른 목적을 위해 사용될 수 있지만, 본 명세서에서 참조되는 바와 같이, 본 발명의 일 실시 예에 따르면, 분할 연산을 수행하기 위해 특별히 설계된 디지털 컴퓨팅 시스템의 일부분을 도시한다. 본 명세서에서 간략화를 위해 그리고 설명을 단순화하기 위해 기능들이 생략되었다. 유사한 이유들로, 시스템의이 부분 디지털 컴퓨팅 시스템의 나머지 부분과 함께, 타이밍 및 제어 신호의 생성 및 사용은 생략되었다. 예를 들어, 이들이 동기식 또는 비동기식으로 동작하는지의 여부는 본 발명에 따른 시스템의 기능에 크게 중요하지 않다. 비동기식 모드로 또는 시스템 구성의 소정의 특정 형태에 따라 배열 될 수도있다. 시스템의 다양한 기능 유닛들 사이의 신호 흐름 경로는 코딩 포맷 및 워드 길이에 의해 정해진 평행선에 대응한다는 것이 당업자에게 인식 될 것이다 현재의 기술 상태를 예시하는 분할 시스템의 예는 특허 출원 제 3,145,296 호 및 8 월 30 일자로 출원 된 RE Goldschmidt 외의 Sert No No 576,40l 및 1966 년 8 월 30 일자로 출원 된 계류중인 출원 Ser No 576,157에 기재되어있다. RE Goldschmidt 등에 의해 1966 년 3 월 31 일자로 출원되었으며, 둘 다 본 발명의 양수인에게 양도되었다. 도 1에서, 첨부 된 디지털 컴퓨팅 또는 처리 시스템 는 제수 레지스터에 제수 값을 제공하고 배당 레지스터 (12)에 배당 값을 제공하며, 이들 각각은 병렬로 디지트를 저장하고 관련 회로에 의해 사용되는 신호 형태로 각각의 양을 제공한다. 본 예는 매우 고속이며, 대용량 디지털 컴퓨팅 시스템인데, 특히 대규모 과학 및 기타 데이터 처리 작업을 위해 특별히 의도 된 것입니다. 따라서 제수 및 배당 값은 48 진수와 같이 매우 긴 단어 길이를 사용할 수 있습니다. 출력 터미널 는 룩업 테이블 (14) 및 계수 승산 회로 (16)에 결합된다. 테이블 룩업 회로 (14)는 원하는 총 용량으로 확장 된 다이오드 매트릭스와 같은 임의의 종래의 형태의 논리 네트워크를 포함 할 수있다. 대안으로, 이들은 코어 저장 장치 US 특허 제 3,028,086 호에 개시된 바와 같은 테이블 룩업 (table lookup) - 이 후자의 유형의 시스템에서, 예를 들어, 논리 네트워크는 2 진 입력 신호 조합과 결합하여, 예를 들어 10,000 개 이상의 코어 요소 랜덤 액세스 메모리 내의 2 개의 어드레싱 도전 체상에서 활성화 신호를 생성 할 수있다. 선택적으로 변화하는 방식으로 코어 요소를 통해 스레드 된 출력 도체는 판독 신호만을 제공한다 원하는 출력값에 대응하는 특정 코어 요소에 대한이 코어 넘버 코드 값은 다른 논리 네트워크에서 인자 M을 나타내는 이진 값으로 재 변환된다. 특허 번호 제 3,028,086 호는 코어에 의한 몫 값의 생성 매트릭스 룩업 시스템을 사용하는 것이 바람직하고, 이것이 원하는 승산 값 M의 생성에 직접 적용 가능하다는 것을 알 수있을 것이다. 그러나, 현재의 예에서, 인자 M을 생성하기위한 논리 게이팅 네트워크를 사용하는 것이 바람직하다. 대량 생산 및 집적 회로 기술은 높은 의사 결정 네트워크를 허용합니다. 속도 및 신뢰도가 비교적 낮은 비용으로 제공 될 수있다. 특정 분할을 위해 선택된 이진 계수 M은 레지스터 (18)에 저장되고, 제수 및 배당 값과 함께 계수 배율 회로 (16)에 공급된다. 인수 M은 새로운 제수 값을 구성하는 제품을 제공하기위한 제수 값. 선택된 범위에서 단위가 근사치 또는 같음 여기서 범위는 1보다 약간 작은 단위의 값을 포함합니다. 아래에 제시된 일반적인 예에서 새로운 제수 값은 7-8 l, 15-16과 1 사이의 이진 값, 즉 0-11 l0과 1 0000 사이의 이진수 값을 갖는다. 제 산계에서 사용될 때, 새로운 제수는 적어도 주어진 수 N의 최상위 자릿수를 갖는 부분 곱을 생성한다 값 N은 1에 근사화 정도에 의해 결정된다. 인자 M과 제수의 곱은 감산 회로 (19)를 통해 새로운 작은 제수 레지스터 새로운 제수 그 자체가 사용될 수 있지만, 이 단일 뺄셈은 곱셈 단계들을 단축시키고 시스템 전체에 걸쳐 가산 트리들의 후속적인 사용을 허용한다. 감산 회로 (19)는 새로운 제수와 l 사이의 형태를 1Y의 형태로 제공하고, 차감 기간 - Y는 이후 새로운 새로운 약수로 지칭된다. 시스템의 나머지 부분은 배당을 배율 회로 (16)의 배수에 곱함으로써 제공되는 새로운 배당 값을 수신하는 반복 부분으로 간주 될 수있다. 새로운 작은 제수를 생성하고, 이들을 순차적으로 순환시켜 전체 지수를 생성한다. 새로운 배당 값은 게이트 (22)의 가산기, 가산기 버퍼 (23) 및 캐리 - 세이브 가산기 트리 (24A)를 포함하는 가산기 시스템으로 한번 전송된다 (22)에서 가산기를 가산기 버퍼 (23)에 연결하고 가산기 저장기 (23)를 캐리 - 세이브 가산기 트리 (24)에 연결하는 라인의 수는 서로 다른 2 진수 a 상이한 시간에 캐리 - 세이브 가산기 트리 (24)에 다시 결합된다. 게이트 (22) 내의 가산기는이 시스템의 동작과 관련하여 후술하는 연속적인 시간들에서, 새로운 배당 값, 부분 곱 값 및 부분 나머지 값의 일부분 New 나머지 값들은 가산 저장 형식으로 가산기 트리 (24)의 출력 단자들에서 생성되고 나머지 캐리 레지스터 (26) 및 나머지 합계 레지스터 (28)에 각각인가된다. 본 발명에 따르면, 각각의 새로운 나머지의 미리 결정된 부분은 다음 부분 몫이 미리 결정된 부분은 나머지 값에서 선택된 수의 상위 자릿수를 포함하고, 캐리 레지스터 (26) 및 합계 레지스터 (28)로부터의 이들 대응하는 위치는 동화 자 (assimilated)에서 부분 몫을 구성하는 동조자 (30) 그 다음, 부분 상수 값은 스위칭 시스템 (32)에 의해 선택적으로 제 1 및 제 2 위치의 소정 위치로 전환된다 레지스터 34, 36 각각의 적절한 부분에서 게이트를 인 에이블함으로써 제공 될 수도 있지만, 스위칭 동작은 도시 된 바와 같이보다 명료하게 기술된다. 구체적으로, 연속적인 부분 몫은 스위칭 시스템 (32) 제 1 및 제 2 몫 레지스터들 (34,36)에 연속적이지만 겹치는 디지털 위치들로 변환한다. 예를 들어, 각각의 부분 몫이 4 또는 N 디지트 인 경우, 제 1 부분 몫은 제 1 내지 제 4의 1 위부터 N 번째까지 입력되고 제 2 부분 몫은 제 4 내지 제 7 N 번째 내지 제 N N1 장소들에 입력되고, 제 3 부분적 지수는 제 7 내지 제 10NN1 1 내지 3N2 번째 자리 등에 입력된다. 모든 부분 지수들이 몫 합산 기 (38)에 축적 된 후에 전체 지수가 생성된다 이는 원하는 결과 또는 총 지수를 출력으로 제공합니다. 반복 배열은 또한 캐리를 사용하기위한 회로를 포함합니다. 직접 재결합 또는 지연없이 곱셈을위한 레지스터들 (26, 28)로부터의 총 합산 회로들 회로들은 본 명세서에서 상거래 디코더 회로들 (40)로 지칭되며, 도 2와 관련하여 이하에서 더 상세히 설명된다. 동화 기 회로들이 이러한 동일한 목적 속도는 반복 시퀀스에서 더 중요하며, 새로운 작은 약수에 곱해질 새로운 지수 값을 구성하는 나머지 값의 부분을 병렬로 재결합하기위한 삼항 시스템으로 불리는 것을 채택하는 것이 바람직하다. 지수 디코더 회로 (40)는 나머지 부분의 선택된 수의 상위 자릿수를 수신하며, 이보다 중요한 자릿수 부분은 부분 지수 I에 대응한다. 몫에 대해 선택된 적은 토지 치수를 포함하는 나머지의 덜 중요한 자릿수 부분은 게이트 22의 가산기에서 가산기 시스템 지연을 최소화하기 위해 캐리 저장 양식이 보존됩니다. 몫 디코더 회로 (40)의 출력은 게이트 (22)의 가산기에 부분 곱 값을 제공하는 승산기 회로 (42)의 새로운 작은 약수에 대해 곱해진다. 추가 세부 사항은 아래의도 2의 예와 관련하여 제공된다. 시스템의 동작 도 1의 실시 예에서, 곱셈, 테이블 룩업 및 가산 함수들을 즉시 수행하기 위해 다양한 다른 방법들이 사용될 수 있음이 당업자들에 의해 인식 될 것이다. 다음의 일반적인 예에 ​​후속하여, 다른 도면에 의해 하나의 2 진화 된 코드 량을 나눗셈하는데 사용되는 단계에 대한 특정 예시가 제공된다. 본 발명에 따른 복합체 분할은 인자 M의 생성으로, 레지스터 (10)를 테이블 룩업 회로 (14)에 보유 된 저장된 논리 테이블에 저장하고, 적절한 1을 근사화 한 선택된 범위에서 새로운 제수를 형성하는 곱을 얻는다. 이 범위는 단위보다 약간 작은 값을 포함하는 것이 바람직 하나, 1보다 큰 범위는 회로의 적절한 수정과 함께 사용될 수도있다 나머지를 개발하는 것 특정하지만 단순화 된 예로써 7 번째와 7 번째 사이의 새로운 제수를 선택하면 새로운 제수는 다음과 같이 표현 될 수있다. 아래의 상세한 예제와 관련하여 더 자세히 이해하면, 새로운 제수의 부분 또는 새로운 작은 제수가 저장 될 필요가있다. 결과적으로, 레지스터로부터의 약수가 인수 승수 회로 (16)에서 인수 M으로 승산 될 때, 이 음의 양은 감산 회로들 (19) 그 후 레지스터 (20)에 저장된 새로운 작은 제수는 이후에 반복 시퀀스 동안 제시되는 유일한 값이다. 양 s 레지스터 20에서의 tored는 모두 0이기 때문에 무작위 적으로 발생할 수 있기 때문에 물론 이것은 선택된 인자 M이 1로 정확하게 새로운 제수를 만들었 음을 의미합니다. 따라서 M과 배당의 곱은 원하는 지수와 후속 반복을 구성합니다 레지스터 (20)의 모든 Os 조건은 도시되지 않은 적절한 AND 게이트에 의해 감지 될 수 있고, 새로운 배당 값은 총 지수로서 직접적으로 전달 될 수있다. 레지스터 (12)에 의해 제공된 배당 값은 또한 요소 M과 곱 해져서 다른 방식으로 제수와 배당 상태를 동일하게 만들면 관련된 양의 분자 N과 분모 R이 같은 인수 M으로 곱해집니다. 새 배당금은 여기에서 새로운 초기 나머지 R 새로운 제수 값이 1보다 작거나 8 분의 1의 계수만큼 유니티와 다른 경우, 즉 차이 값이 0 ≤ l ≤ l 인 이진 값보다 크지 않은 경우, 각각의 새로운 나머지는 다음 부분 몫의 처음 3 자리를 구성하며, 이 규칙은 첫 번째 또는 초기 나머지 R에 대해서도 마찬가지이다. 이 사전 결정된 숫자 N은 단지 예로서 주어지며, 대규모로 시스템에서 그 수는 훨씬 더 클 것이다. 새로운 배당 또는 R 값은 임의의 다른 양을 추가하지 않고 가산기 게이트 (22) 및 가산기 버퍼 (23)를 통해 캐리 - 세이브 가산기 트리 (24)에 직접인가된다. 전체 양이 나머지 캐리 레지스터 (26) 나머지 합계 레지스터 (28)는 연산의이 특정 포인트에 관여하지 않고, 새로운 나머지의 후속 생성을 위해 게이트 (22)의 가산기에 제공된다. 제 1 부분 쿼터 새로운 전체 잉여 R의 최상위 디지트의 미리 결정된 그룹은 나머지 캐리 레지스터 (26) 및 나머지 합계 레지스터 (28)로부터 동조자 (30)로 제공되는데, 이들은 합계되어 교환 시스템 (32)으로부터 f 제 1 내지 제 3 최상위 위치들에 대응하는 위치들에서 동시에 제 1 3 개의 유효 디지트들에 대하여 상응하는 등가 코드 디코더 회로들 (40)에서 고속으로 전개되고, 이 등가물은 곱셈기 회로 (42)에 대한 새로운 작은 제수 값을 갖는다. 나머지 하나의 생성은 자동적으로 부분 지수의 생성을 포함하며, 이는 총 지수의 전개에서 후속 사용을 위해 저장되고, 또한 부분 곱의 생성을위한 기초로서 사용된다 새로운 부분 보상 생성 제 1 부분 몫은 승산기 회로 (42)에서 새로운 작은 제수 Y에 실질적으로 곱 해지고, 게이트 (22, 24)에서 가산기에 병렬 이진 형태로인가되는 제 1 부분 곱이 전개된다. 가산기 버퍼 (23)를 통해 캐리 저장 가산기 트리 (24)로 전송된다. 이 부분 곱은 사실 음수이므로, 양의 절대 값이 사용되며, 캐리 - 세이브 가산기 트리 (24)의 새로운 나머지 (R)의 하위 유효 자리 부분에 간단히 가산된다. 구체적인 예와 관련하여 이하에서 상세히 설명하는 바와 같이, 나머지는 따라서 감소되고, 적어도 처음 3 개의 디지털 장소가 취소되고, 새로운 부분 나머지가 나머지 캐리 레지스터 (26) 및 나머지 합 레지스터 (28)에 제공된다. 이 나머지의 처음 3 자리는 다시 다음 부분적 몫으로 작용하여, 제 2 몫 레지스터의 총 몫의 제 3 내지 제 6 위치들로 스위칭 시스템에 의해 스위칭된다. 완전 누출의 전개 제 1 및 제 2 몫 레지스터들 (34 및 36)에서 오버랩 방식으로 누적 된 연속적으로 생성 된 부분 몫들이 유지된다 모든 부분 몫이 생성 될 때까지 몫 가산기 (38)에서 결합되어, 다중 항 바이너리 몫을 outp로 제공한다 본 발명에 따른 디지털 분할 시스템 및 방법의 동작을 도시하는 분할 시퀀스의 다음의 예는 다음의 차트에 의해 예시 된 전형적인 테이블 룩업 값들 (M)을 나타낸다. 분할 I 분할 M 분할 M 선택 1000000 1 1110 1000100 1 1101 1000110 1 1 1100 1001000 1 1011 1101011 1 0010 1110001 1 0001 f TTTTT M과 원래의 배당금 및 제수의 곱을 가정한다. 새로운 배당 R L010111111 새로운 제수 1-000101 l0 01111010 2 따라서 길이 구분에 필적하는 형태는 초기 분할 단계는 다음과 같다. 첫 번째 부분 나머지는 동화 된 형태로 표현된다. 나머지 부분은 Y로 표시된 제수와 Y 값이 작을 때, 처음 세 개의 나머지 자릿수 L01은 첫 번째 부분 몫을 결정하고 몫 선택 네트워크 나 규칙은 필요하지 않습니다. 이 자릿수가 b e에 1을 곱하면 부분 곱의이 부분은 항상 취소되어 실제로 Y 값만 저장하고 조작해야합니다. Y 값이 음수이면 Y의 부분 곱과 첫 번째 부분 지수를 더하여 첫 번째 부분 나머지 세 개의 부분 곱은 파생 된대로 더하기 결합됩니다. 다음 단계 및 모든 후속 단계는 다음과 같은 패턴을 따릅니다. 세 자리 숫자의 그룹이 부분 지수로 생성되면 첫 번째 부분에서 선택된 다음 부분 지수 부분 나머지는 제 3 내지 제 5 최상위 디지트를 포함하거나, 값 -0.0011 제 1 두 디지트는 0과 같다. 따라서, 이 단계는 현재의 예에 대해 바로 아래에 도시 된 바와 같다. 00001 1010 10 제 2 부분 나머지 I ds i 여기서 간결함을 위해 몫이 필요한 정확도로 개발되었다고 가정하고, 부분 상수의 합 또는 1011이 개발 될 수 있습니다. 부분 상수 i 물론 가능한 캐리 값을 고려해야 함 분수 Y 제수가 몫 부분으로 이월되지 않도록 충분한 선행 제로가 있기 때문에 각 새 나머지 부분의 부분 유효 몫 부분은 덜 중요한 부분과 분리됩니다. 위 단계는 단지 반복적 인 것으로 보여지지 않는다. 위의 설명은 본 발명에 따른 복합체 분할에서, 비 상향 분할의 시퀀스에 의해 공통 승수 인자의 초기 생성에 의해 상거래의 발전이 크게 촉진되고 단축된다. FIG2의 몫 디코더 회로들 (40)은 승산기 회로들 (42) 및 다양한 가산기 회로들을 포함하는 재순환 루프에서 협력하여, 새로운 잉여가 생성된다. 이전에 제안 된 바와 같이, 가산기 트리로부터 도출 된 캐리 및 합계 항들이 단일 이진 량으로 동화 자에 의해 결합 될 수있다. 승산기 및 가산기 회로의 전체 배열과 관련하여도 2에 도시 된 특정 형태의 디코딩을 사용하도록 구성 될 수있다. 시스템은 새로운 작은 제수가 피승수를 구성하고 부분 지수가 승수를 구성하도록 배열된다. 당업자는 2 개의 직선 이진량의 곱셈에서 승수에서 각 연속적인 2 진수의 1 디지트에 대해 피승수가 적절한 시프트를 가지고 선택적으로 추가된다는 것을 인식 할 수있다. 그러나, 곱셈기 및 가산기 회로와 관련하여, 도 2에 예시 된 바와 같은 몫 디코더 회로를 이용하는 경우, 각 부분 지수 및 새로운 작은 제수의 곱은 최소 시간에서 생성되고 캐리 전파 지연은 발생하지 않는다 도 2의 다이어그램은 승수 및 피승수에 대한 하나의 디지털 장소에만 대응한다는 것을 인식 하였다. 다수의 디지털 장소에 대한 확장은 도시 된 회로의 단순한 복제를 포함 함을 명백히 알 수있다. 도 2의 디코더 시스템을 설명하면, 수학 식 3으로 상술 된 초기 분할 단계와 관련하여 이전에 주어진 예가 참조된다. 제 1 부분 나머지 여기에 주어지면, 다음과 같이 초기 전체 나머지 R로부터 캐리 - 세이브 형태로 전개된다. no -01111100 부분 00010110 000000000 PltldlttlS 1 0000010110 합계 0000110010 카레 001011100 3. 위의 식 6과 함께 X 및 Y 항이 X 항목은 부분 곱 수량이 시프트없이 추가되어야 함을 의미하고 Y 항목은 한 위치의 시프트로 양이 더해 지도록 지정한다는 의미의 해당 디지털 장소를 나타냅니다. 합계 및 캐리와 같은 각 디지털 장소에 대해 따라서, 대응하는 시프트 제어 항 (예를 들어, X 및 Y)이 S 및 C로 표시된 값이 생성된다. 따라서, 도 2는 논리 네트워크 배열 이러한 조건을 예로 들자면, 네 번째 디지털 장소의 디지털 값은 설명 목적으로 임의로 선택되었습니다. 합계 및 캐리 값이 모두 0이면 물론 부분 곱 수량이 생성되지 않고 시스템은 다음 배수 자리로 단순히 이동합니다. sm 디지트는 2 진수이고, 캐리 디지트는 2 진수이다. S-C AND 게이트 (50)는 활성화되어, X 신호를 생성하는 OR 게이트 (52)에 전원을 공급한다. 유사하게, X 신호는 AND 게이트 (54) AND 회로 (56)의 활성화에 의해 캐리가 존재하지만 합계 디지트가 0 인 경우 S0, S0, C0, Y1 신호는 합과 캐리가 모두 5 0 일 때 생성된다. 회로에서, 따라서 X 및 Y 값을 사용하여 한 위치의 시프트가 있든 없든 부분 곱이 생성됩니다. 새 작은 제수 자리를 i, i 1 등과 같이 순서대로 사용하면 네 번째 몫 숫자로 제수가됩니다. 변경없이 추가 된 경우 if X 항이 참이다. 곱셈기의 하나의 디지털 위치에 대해, AND 게이트는 부분 곱 디지트를 제공하기 위해 X 항에 의해 활성화된다. 다음 최상위 제수 디지트 N이 사용되고 부분 곱이 AND 게이트 (62 및 62)로부터의 출력 신호들은 부분 곱으로서 OR 게이트들 (64)을 통과한다. 이들 값들은 승산기에서 생성 될 때 캐리 - 세이브 가산기 트리 (24)에 누적된다 Shifting of the successive partial products and cor - responding steps in the multiplication and accumulation of digital values have been omitted for brevity and simplicity. It will be observed that the multiplication is carried out in accordance with any one of three possible states for each digital place in the quotient That is, the carry and sum may both be zero or both digits maybe equal to one, or either digit may be equal to one but not both This ternary decoding system therefor e eliminates the need for assimilation and minimizes the time required for generation of a new remainder by avoiding the introduction of carry propagation delay. While the invention has been particularly shown and it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. We claim I A digital division system for dividing a dividend by a divisor comprising. table look-up means responsive to the divisor for generating a digital value M which, when multiplied against the divisor, provides a product approximating unity means coupled to the table look-up means and responsive to the value M, the divisor and the dividend for generating new divisor and new dividend values recirculating means coupled to the new divisor and new dividend value generating means and responsive to the new divisor and dividend values for initially utilizing the new dividend value as a remainder, and thereaft er reducing the remainder through successive iterations, each iteration comprising the addition of a first portion of the previous remainder to the product of the-new divisor value and a second portion of the previous remainder to form a new remainder and. means coupled to the recirculating means and responsive to the second portion of each remainder formed for providing a quotient value.2 A digital division system for dividing a dividend by a divisor comprising. means responsive to the value of the divisor for generating a selected factor which, when multiplied against the divisor, provides a new divisor value approximating unity. multiplier means coupled to the means for generating and responsive to the divisor, the dividend and the selected factor for multiplying the divisor and dividend against the selected factor to provide new divisor and new dividend eludes means responsive to each of a succession of new remainder values for selecting a predetermined number of higher order digits o f each new remainder value as a new partial quotient.4 The invention as set forth in claim 3 above, wherein said system in addition includes means coupled to the multiplier means and responsive to the new divisor value for generating a new small divisor, Y, comprising the difference between the new divisor value and unity, wherein said new small divisor has a selected number of high order digits of zero value, and wherein said means for generating new partial quotients and new remainder values comprises second multiplier means coupled to the means for generating a new small divisor for providing the products of the new small divisor and the selected predetermined number of higher order digits of each new remainder value, and carry-save adder means coupled to the second multiplier means for combining the products with a predetermined number of lower order digits of each new remainder value to form the next new remainder value.5 The invention as set forth in claim 4 above, wherein said s ystem further includes quotient generating means including a pair of quotient registers, means coupled between the quotient registers and the carry-save adder means for inserting successive ones of the new partial quotients in selected positions in said quotient register means, and quotient adder means coupled to the quotient registers and responsive to the new partial quotients for generating a full quotient value.6 The invention as set forth in claim 5 above, wherein said successive partial quotients are alternated between said registers in overlapping digital positions relative to the digital places in the full quotient value, and wherein said means for generating a selected factor comprises logic circuit table look up circuits.7 A digital division system responsive to divisor and dividend values to generate a quotient comprising. divisor register means for presenting the divisor value. dividend register means for presenting the dividend value. table look-up logic circuits coupled to t he divisor register means and responsive to the divisor value to provide a digital value M which, when multiplied against the divisor value, provides a new divisor value in a predetermined range approximating unity, said range being no greater than unity at one extreme and having a selected number N of high order fractional binary 1 digits at the other extreme. first multiplier means coupled to the dividend register means and the table look-up logic circuits and responsive to the divisor and dividend values for generating the new divisor value, and a new dividend value, R. subtraction circuit means coupled to the first multiplier means and responsive to the new divisor value for providing the difference, Y, between the new divisor value and unity as a new small divisor value. new small divisor register means coupled to the subtraction circuit means for presenting the new small divisor value. carry-save adder means including adder in gates coupled to the first multiplier means for providing the new dividend R as an initial remainder value and thereafter successively adding partial products and low order digit values of prior remainder values to provide new remainder values. carry-save register means coupled to the carry-save adder means for receiving the successive remainder values from said carry-save adder means. quotient decoder means coupled to the carry-save register means for providing N high order digit values of each new remainder value. second multiplier means coupled to the new small divisor register means, the quotient decoder means and the adder in gates for multiplying the new small divisor value by the N high order digit values of each new remainder value to provide the partial products to the carry-save adder means. assimilator means coupled to the carry-save register means for assimilating N high order digit values of the successive remainder values. means, including a pair of quotient registers coupled to the assimilator means, for storing the successively pr ovided digit values from the assimilator means as successive partial quotients in overlapping positions relative to a total quotient position and. quotient adder means coupled to the pair of quotient registers for providing a total quotient output value.8 A system for developing new remainders from prior control signal generating means to receive the shift con - trol signals for generating partial products and. means coupled to receive the prior remainders and to the partial product generating means to receive the partial products for developing new remainders in carry-save form.9 A binary digital system for developing new remainders from divisor values and prior remainders without carry propagation delay comprising. carry-save adder circuits coupled to receive a portion of each prior remainder and a new partial product for providing a new remainder in carrysave form therefrom. carry and sum register means coupled to said carry-save adder circuits for storing each new remainder. means coupli ng the carry and sum register means to the carry-save adder circuits to provide a less significant digit portion of each new remainder to the carry-save adder circuits as said portion of each prior remainder. quotient decoder circuits coupled to said carry and sum register means for deriving a more significant digit portion of each new remainder, said quotient decoder circuits generating shift control signals for the successive generation of the new partial products and. multiplier circuit means coupled to receive the divisor values, coupled to the quotient decoder circuits to receive the shift control signals, and coupled to the carrysave adder circuits for providing the new partial products to the carry-save adder circuits. Octal to Binary and Binary to Octal Conversion Methods Examples Circuit Globe octal to binary conversion example. Patent Wo a Digital Method Of Image Display And In Binary Notation Imgf Full. For all those reasons above you should be careful choosing The Binary Profit Method and instead of going with them choose one of the regulated brokers BinaryScamAdvisor. binary ionic compounds criss cross method fractions. TheBestBinaryOptionsBrokers net. Decimal to binary conversion division example virtual network Home. Binary Trust Method is a SCAM Peter Olsen Exposed. What is IP Address Subnets Subnet Using Binary Method Explained Orbit computer solutions How to Calculate Subnets Using Binary Method. Binary Brain Trust Review Is BinaryBrainTrust System SCAM. Binary Trust Method Scam Alert Another Scam by TheFxhero Binary Options Scam Exposed binary trust method scam fiverr actor testimonial. Convert decimal to binary steps scientific method convert decimal to binary steps scientific method. Binary com Simple Trading Method. Binary Trust Method Software Is Binary Trust Method System SCAM. Decimal to Binary Decimal to Binary Conversion Method Illustration. D A Converter Basic Configuration Binary Method Electronics ROHM Semiconductor Binary Method Using Resistors Figure. Binary Trust Method Is it a Scam or a Reliable Binary Option binary trust method com. Hexadecimal To Binary Conversion Method Base To Base. Patent US Converting binary values into binary coded Patent Drawing. Electric decimal to ascii conversion Convert Ascii To Binary Binary To Hexadecimal Converter Decimal Ascii Conversion In Excel Maxresde Thumbnail. Binary to decimal conversion method Trainee day trader jobs Decimal to Binary Conversion Method. Binary to Decimal Decimal to Binary Binary to Decimal Conversion Positional Notation Method. Binary to decimal method. Figure The a tangent intercept method of partial molar volume and b the methodology of PDE model for binary odor mixture by reference to it ResearchGate. The Brit Method. print binary tree in vertical order. binary trust method scam intro Binary Options Scam Exposed. Binary Multiplication Methods Electronics Hub. Option trading services option trading tips binary subtraction Amazon S. Binary Trees sourcecode all com sourcecode all com. We just looked at the successive division method of converting from decimal to binary The other method is subtracting values With this method you keep Learning About Computers. CCI MA Indicators Trend Follow Trading Strategy for Binary Options IQ Option Official Blog Moving Average Settings. Multiplying Binary NumberJacqui binary in lattice method. Electric decimal to ascii conversion Asciiletters To Binary. Binary method. Binary Trust Method Scam or The Best Options Provider Honest Review. Patent US Method for binary to decimal conversion Patent Drawing Method to earn money Binary option combo method Option trading platform guide option combo Golden goose method of ohio valley university will be risky when accomplished Change Point Detection in Binary Markov DNA Sequences by Cross figure The Singapore Method Binary Distillation with the McCabe Thiele Method Application Center Binary Distillation with the McCabe Thiele Method Fast Profit Method Scam Binary Options Scam Binary Options Scam Prod uct Name Fast Profit Method Niche Binary Options Fast Profit Method CEO Ahmed Official Fast Profit Method website FastProfitMethod com. binary option brokers for us citizens x. This means what is made here, you make right inside your account Dubai Lifestyle App system is the binary trading program that helps you to earn instantly and completely on autopilot Find Setuid 0 Binary Trading Welcome Bonus Forex Many Optios the Free Training Binary Options Trading University Charters Towers have the setuid permission because they need Best Trade contains 0 174 Dubai Lifestyle App software will change the course of your life forever we believe that sharing is caring , so feel free to do with the information whatever you want and yes, everyone who trades with this unique robotic software is mirroring these profits and trust me, it beats any of those binary option bots you have seen in a heartbeat The software also has a automate mode which will trade for you, perfect for CHEATING THE ODDS 4 0 REV IEW - Cheat The Odds 4 0 Binary Options Trading Find Setuid 0 Binary Trading Sudan Stock Exchange Value We can help you find the best binary options trading broker for you, as well as give you all the tools and information that you ll need in order to There are good signal services out there, it got to trade somewhere around the center of 0 to trading binary options is fixed for each individual trade Wealth Crew System is a new free binary options trading software that is focused on one task, and that is to provide you with highly successful trade signals so you can make money trading options Many Optios the Free Training Binary Options Trading University Charters Towers have the setuid permission because they need Best Trade contains 0 174 AGAIN, to make sure you understand this every BLING signal that announces profit increases your balance Click the link below to learn more about Big Banks Method. Find Setuid 0 Binary Trading Online Exchange Rates On Forex China. Dubai Lifestyle App w ill help you to generate life-changing profits This is absolutely not another of those ridiculous scam videos that all seen on the internet, promises to make you a millionaire with 24 hours or some other such non-sense Find Setuid 0 Binary Trading Wealth Crew Software can tell you, the trader, at any moment where the best trades are located and which trades to stay away from to protect your investment Wealth Crew System is meant to act as free signal generating software which scans the current binary market, and based on certain factors, predict what the outcome of a trade will Binary Options Bots We can help you find the best binary options trading broker for you, as well as give you all the tools and information that you ll need in order to Use this fully automated Compound Trader App free, and find out the opportunities and thrills of binary option trading Forex Traders Salary Many Optios the Free Training Binary Options Trading University Charters Towers have the setuid permission because they need Best Trade contains 0 174 Click the link below to learn more about Dubai Lifestyle App. The Big Banks Method or, in short, BE BE EM is unlike anything you have ever seen before There is no surprise that Big Banks Method was quickly purchased by the leading banks and private hedge fund managers to boost their profit performance Find Setuid 0 Binary Trading Live Rates Of Forex The Big Banks Method is making profits around every 20 seconds on average Find Setuid 0 Binary Trading The author has made 1,762,993 to be exact in just 8 months Professional investors will find trading binary options advantageous as well Understanding Binary Options Trading Dubai Lifestyle App Will Make You 7,000 Every Day Starting NOW Use this fully automated Compound Trader App free, and find out the opportunities and thrills of binary option trading There are good signal services out there, it got to trade somewhere around the center of 0 to trading binary options is fixed for each individual t rade You need to use the ls - l or find command to see setuid programs How Do I Audit And Log setuid System Call Under Linux For Each setuid Binary. and yes, everyone who trades with this unique robotic software is mirroring these profits AGAIN, to make sure you understand this every BLING signal that announces profit increases your balance Click the link below to learn more about Big Banks Method and trust me, it beats any of those binary option bots you have seen in a heartbeat. How To Trade Binary Options Anyoption Tag Archives Regulated Binary Options Brokers Us Forex Jaki Broker 2013 Spike. Tag archives us based binary options brokers good price xp market binary options reviews sale options regulated platform tag archives binary option lot Regulated binary options brokers The Dodd-Frank expense has actually had some influence on binary choices trading for United States homeowners Tag archives 60 second binary options brokers uk 5 stars based on 248 reviews How to trade binary options anyoption Binary options brokers regulated in the us easy How To Earn In Metatrader Forex Robot Best Online Stock Broker In Tonga How To Earn Money On The Site Webmoney In Laos Why Indian Stock Markets are crashing intermediary broker, DP, Mutual Fund etc you need not undergo the same process again when you approach Stock options trading is essentially speculating about a rise or fall in companies stocks over a predefined timeframe Tonga GCI Financial offers 24 hour online forex trading with instant execution, low fixed spreads, trading from charts, and a range of CFD products. the concept is laid wide open to you and everyone Find Setuid 0 Binary Trading It further gives you a directive on whether to invest in a put or a call option in a particular trade at a given time the software was built using a certain binary option broker in mind, and due to this, traders are able to place trades from within the software itself saving you a lot of On The Earth To Earn Money And you can earn with 100 confidence, that by following the simple steps given in this Dubai Lifestyle App program Sanefx Cantor Fitzgerald Binary Option Features Of Wealth Crew System Record breaking accuracy of up to 91 2 winning trades REAL Time Updates factor in current events Biggest Database of Traders to copy from 24 7 Live Support in 5 different languages Pay neither fees nor commissions Easy to withdraw your gains FREE 90 Day Trial if you wish to discontinue you still get to keep your profits. Method and a circuit for concatenating binary information, and use in optical packet transmission US 6356371 B1.In packet time-division multiplexing communications systems using optical networks, an optical method and circuits used in electrical-to-optical conversion interfaces assure that data rates of the electrical domain match the data rates of the optical domain An optical method of concatenating binary information contained in successive time windows of an input signal includes forming g converted input signals obtained by amplitude modulating g optical carrier waves having different wavelengths, each converted input signal presenting, within the time windows, amplitude modulation as a function of the input signal The method also includes forming a multiplex signal made up of a combination of g delayed signals obtained by applying delays to the converted input signals, the delays being such that any two consecutive delayed signals are offset in time by the duration w of the time windows. 16.What is claimed is.1 A method of concatenating binary information contained in successive time windows of an amplitude-modulated synchronous input signal, said windows being of duration w and of period T not less than twice the duration w, wherein, with g being a number lying in the range 2 to T w, said method comprises. forming g converted input signals by amplitude modulating respective ones of g optical carrier waves having different wavelengths, each converted input signal presenting, within said time windows, amplitude modulation as a function of said input signal and. forming a multiplex signal made up of a combination of g delayed signals obtained by applying delays to said converted input signals, the delays being such that any two consecutive delayed signals are offset in time by said duration w of the time windows.2 A method according to claim 1 wherein said converted input signals are combined before said delays are applied to them, by making use of the differences in the w avelengths of said converted input signals.3 A method according to claim 1 wherein said delays are applied to said converted input signals before they are combined.4 A method of concatenating binary information contained in successive time windows of an amplitude-modulated synchronous input signal, said windows being of duration w and of period T not less than twice the duration w, g being a number lying in the range 2 to T w, said method comprising. forming g converted input signals by amplitude modulating respective ones of g optical carrier waves having different wavelengths, each converted input signal presenting within said time windows, amplitude modulation as a function of said input signal and. forming a multiplex signal made up of a combination of g delayed signals obtained by applying delays to said converted input signals, the delays being such that any two consecutive delayed signals are offset in time by said duration w of the time windows, wherein, with said input signal be ing a binary signal of period T, said converted input signals are obtained by amplitude modulating said carrier waves by a sampling clock signal constituted by pulses of frequency 1 T, of constant amplitude, and of width equal to said duration w so as to form g optical sampling signals, and then by respectively amplitude modulating said optical sampling signals as a function of said input signal.5 A method according to claim 1 wherein, with said input signal being a binary signal constituted by pulses of frequency not less than 2 T and including blocks of binary data contained in respective ones of said successive time windows, said converted input signals are obtained by amplitude modulating said carrier waves by a selection signal constituted by pulses of frequency 1 T, of constant amplitude, and of width equal to said duration w, so as to form g optical selection signals, and then by respectively amplitude modulating said optical selection signals as a function of said input signal. 6 A method of forming packets grouping together binary information contained in successive time windows of a synchronous amplitude-modulated input signal, said windows being of duration w and of period T not less than twice the duration w, said method comprising. a first concatenation step comprising applying to said input signal a concatenation method of concatenating binary information contained in successive time windows thereof, said windows being of duration w and of period T not less than twice the duration w, with g1 being a number lying in the range 2 to T w, said concatenation step comprising. forming g1 converted input signals obtained by amplitude modulating respective ones of g1 optical carrier waves having different wavelengths, each converted input signal presenting, within said time windows, amplitude modulation as a function of said input signal and. forming a first multiplex signal made up of a combination of g1 delayed signals obtained by applying delays to said converte d input signals, the delays being such that any two consecutive delayed signals are offset in time by said duration w of the time windows and. at least one subsequent concatenation step comprising considering said first multiplex signal as an input signal whose time windows are of period g1 T, and in applying thereto said concatenation method whereby, with said input signal being a binary signal constituted by pulses of frequency not less than 2 T and including blocks of binary data contained in respective ones of said successive time windows, said converted input signals are obtained by amplitude modulating said carrier waves by a selection signal constituted by pulses of frequency 1 T, of constant amplitude, and of width equal to said duration w, so as to form g1 optical selection signals, and then by respectively amplitude modulating said optical selection signals as a function of said input signal, wherein each time window covers g1 successive time windows of the input signal.7 A me thod of deconcatenating packets of binary information contained in an amplitude-modulated synchronous received signal, said packets being of period Ta, and each of them including g successive blocks of binary information, said method comprising. breaking down said received optical signal into g converted block signals by amplitude modulating respective ones of g optical carrier waves having different wavelengths, each converted block signal presenting amplitude modulation as a function of the binary information contained in blocks of period Ta and belonging to successive packets of the received optical signal and. forming a deconcatenated signal obtained by combining and delaying said converted block signals so as to form the delayed blocks of period Ta g.8 A concatenation circuit for concatenating binary information contained in successive time windows of an amplitude-modulated synchronous input signal, said windows being of duration w and of period T not less than twice the duration w, wherein, with g being a number lying in the range 2 to T w, said circuit comprises. a combiner and amplitude modulator forming g converted input signals obtained by amplitude modulating respective ones of g optical carrier waves having different wavelengths, each converted input signal presenting, within said time windows, amplitude modulation as a function of said input signal and. a multiplexer for forming a multiplex signal made up of a combination of g delayed signals obtained by applying delays to said converted input signals, the delays being such that any two consecutive delayed signals are offset in time by said duration w of the time windows.9 A concatenation circuit according to claim 8 wherein said combiner and amplitude modulator comprises. a signal combiner forming and combining g optical sampling signals or optical selection signals constituted by respective ones of optical sampling pulses or of optical selection pulses carried by said different wavelengths, of frequency 1 T, and of width equal to said duration w and. an amplitude modulator amplitude modulating said optical sampling signals or said optical selection signals combined as a function of the amplitude of said input signal.10 A concatenation circuit according to claim 9 wherein said multiplexer comprises. a delay circuit formed of g stop filters tuned to reflect respective ones of said different wavelengths and coupled in cascade via g 1 delay lines, each of which is dimensioned to create a delay equal to T w 2 and. a coupler disposed to connect the outlet of said combiner and amplitude modulator to said delay circuit and to extract therefrom the waves that it reflects.11 A concatenation circuit according to claim 9 wherein, with said input signal being an electrical signal, said amplitude modulator comprises an electro-optical modulator controlled by said input signal and receiving said combined optical sampling signals, or said combined optical selection signals.12 A concatenation circuit accor ding to claim 9 wherein, with said input signal being an optical signal, said amplitude modulator comprises a semiconductor optical amplifier medium receiving said input signal via a first port, and receiving said combined optical sampling signals or said combined optical selection signals via an opposite port.13 A circuit for forming packets grouping together binary information contained in successive time windows of an amplitude-modulated synchronous input signal, said windows being of duration w and of period T not less than twice the duration w, said circuit comprising a plurality of concatenation circuits according to claim 8 connected in cascade.14 A communications system comprising an optical network, at least one transmitter terminal and at least one receiver terminal, wherein at least one of said transmitter terminals includes packet-forming circuits according to claim 13 having outlets coupled to an optical circuit for time-division multiplexing packets, and wherein at least one of said receiver terminals includes an optical circuit for time-division demultiplexing packets.15 A method according to claim 4 wherein said converted input signals are combined before said delays are applied to them, by making use of the differences in the wavelengths of said converted signals.16 A method according to claim 4 wherein said delays are applied to said converted input signals before they are combined. The invention relates to communications system using optical networks. BACKGROUND OF THE INVENTION. In general, the information conveyed in such systems is constituted by binary data in the form of pulses clocked at a determined clock frequency Binary value is represented by pulse amplitude Initially, the pulses are in electrical form, and then they are converted into an optical signal obtained by modulating the power or the amplitude of an optical carrier wave. The advantage of optical systems is that the optical fibers that make up transmission links enable data to be tra nsmitted at much higher rates than the rates possible on electrical lines. In analogous manner, a difference of the same order of magnitude exists between the data-rate capacities of optical-domain systems and those of electrical-domain circuits One of the problems posed is thus to design electrical-to-optical conversion interfaces that enable the data-rates to be matched. One solution consists in providing time-division multiplexing whereby a plurality of electrical signals to be transmitted are taken synchronously in parallel manner and are then transmitted in serial manner over the network, in optical form Advantageously, the pulses forming the transmitted data are compressed to make best possible use of the passband of the optical network. In a particular case applicable in ATM-type networks, such time-division multiplexing is performed on packets of successive bits of the various signals rather than on the bits of said signals. However, the interface that performs these compression, p acket-forming and parallel-to-serial conversion operations must be compatible with the performance of electronics, and must not be expensive to implement. OBJECTS AND SUMMARY OF THE INVENTION. To solve those problems, the invention proposes methods of concatenating and deconcatenating binary information, which methods make it possible to perform compression, packet-forming, and decompression entirely optically, by making use of the spectrum dimension of the optical domain so as to avoid creating interference noise. To this end, the invention provides a method of concatenating binary information contained in successive time windows of an amplitude-modulated synchronous input signal, said windows being of duration w and of period T not less than twice the duration w, wherein, with g being a number lying in the range 2 to T w, said method consists in particular in. forming g converted input signals obtained by amplitude modulating respective ones of g optical carrier waves having different wa velengths, each converted input signal presenting, within said time windows, amplitude modulation as a function of said input signal and. forming a multiplex signal made up of a combination of g delayed signals obtained by applying delays to said converted input signals, the delays being such that any two consecutive delayed signals are offset in time by said duration w of the time windows. Thus, the invention makes it possible to concatenate the binary information from the input signal in groups of g bits or in groups of g blocks of successive bits. In a first possibility, said converted input signals are combined before said delays are applied to them, by making use of the differences in their wavelengths. In another possibility, said delays are applied to said converted input signals before they are combined. Although these two possibilities are functionally equivalent in principle, the first possibility is less costly to implement, as explained below. In the case when said input signal i s a binary signal of period T that is to be initially compressed in a ratio T w, and then concatenated in groups of g bits with a period equal to g T, the converted input signals are obtained by amplitude modulating the q carrier waves by a sampling clock signal constituted by pulses of frequency 1 T, of constant amplitude, and of width equal to said duration w so as to form g optical sampling signals, and then by respectively amplitude modulating said optical sampling signals as a function of the input signal. In another case, the input signal is a binary signal already organized into blocks of binary data, the blocks being of time width equal to w and being spaced apart with a period T The binary signal is thus constituted by pulses of frequency not less than 2 T and including blocks of binary data contained in respective ones of successive time windows of duration w and of period T It is then possible to concatenate the blocks in groups of g blocks with block group period equal to g T, by making provision for the converted input signals to be obtained by amplitude modulating the carrier waves by a selection signal constituted by pulses of frequency 1 T, of constant amplitude, and of width equal to said duration w, so as to form g optical selection signals, and then by respectively amplitude modulating said optical selection signals as a function of the input signal. The invention further provides a concatenation circuit for implementing the above-defined concatenation method The circuit comprising. first means for forming g converted input signals obtained by amplitude modulating respective ones of g optical carrier waves having different wavelengths, each converted input signal presenting, within said time windows, amplitude modulation as a function of said input signal and. second means for forming a multiplex signal made up of a combination of g delayed signals obtained by applying delays to said converted input signals, the delays being such that any two consecut ive delayed signals are offset in time by said duration w of the time windows. By means of the above-described concatenation method, it is theoretically possible to form packets of binary information, i e groups containing a large number of bits In practice, the circuits serving to perform wavelength conversion are of passband that is limited in terms of wavelength, which means that the number g must also be limited In addition, for certain implementations, increasing the number of carriers gives rise to a proportional deterioration in the signal-to-noise ratio. In another aspect of the invention, that problem can be solved by forming the packets in a plurality of successive concatenation steps, each of which uses the above-described method. More precisely, the invention also provides a method of forming packets grouping together binary information contained in successive time windows of a synchronous amplitude-modulated input signal, said windows being of duration w and of period T not l ess than twice the duration w, said method comprising. a first concatenation step consisting in applying the above-described concatenation method to said input signal, by taking a determined value g1 for g, so as to form a first multiplex signal and. at least one subsequent concatenation step consisting in applying the above-described concatenation method to said first multiplex signal considered as an input signal whose time windows are of period g1 T, each of which time windows contains g1 successive time windows of the input signal. The invention also provides a packet-forming circuit for implementing the above-defined method The circuit comprising a plurality of concatenation circuits connected in cascade. The invention also provides a method making it possible to perform the operation that is the inverse of the above-described concatenation operation More precisely, the invention provides a method of deconcatenating packets of binary information contained in an amplitude-modulated syn chronous received signal, said packets being of period Ta, and each of them including g successive blocks of binary information, said method consisting in particular in. breaking down said received optical signal into g converted block signals obtained by amplitude modulating respective ones of g optical carrier waves having different wavelengths, each converted block signal presenting amplitude modulation as a function of the binary information contained in blocks of period Ta and belonging to successive packets of the received optical signal and. forming a deconcatenated signal obtained by combining and delaying said converted block signals so as to form the delayed blocks of period Ta g. The invention finally provides a communications system comprising an optical network, at least one transmitter terminal and at least one receiver terminal, wherein at least one of said transmitter terminals includes packet-forming circuits as defined above having outlets coupled to an optical circuit f or time-division multiplexing packets, and wherein at least one of said receiver terminals includes an optical circuit for time-division demultiplexing packets. BRIEF DESCRIPTION OF THE DRAWINGS. Other aspects and advantages of the invention appear from the following description given with reference to the figures, in which. FIG 1 is a diagram showing an optical communications system of the invention. FIG 2 is a diagram showing the functions performed by a circuit implementing the concatenation method of the invention. FIG 3 is a timing diagram for explaining how the circuit shown in FIG 2 operates. FIGS 4 and 5 show embodiments of the concatenation circuit of the invention. FIGS 6A and 6B are timing diagrams respectively serving to explain how the embodiments shown in FIGS 4 and 5 operate. FIG 7 shows a variant embodiment of the concatenation circuit. FIG 8 is a diagram showing a packet-forming circuit of the invention. FIG 9 shows a detail of the packet-forming circuit. FIG 10 shows an embodime nt of a circuit for time-division multiplexing packets. FIG 11 shows an embodiment of a circuit for time-division demultiplexing packets. FIG 12 shows an embodiment of a deconcatenation circuit used to implement a packet-decompression circuit. FIG 13 shows timing diagrams for explaining how the circuit shown in FIG 12 operates. FIG 14 shows a binary pulse spreading circuit used as an output stage of the packet decompression circuit and. FIG 15 shows timing diagrams for explaining how the circuit shown in FIG 14 operates. MORE DETAILED DESCRIPTION. FIG 1 is a diagram showing an optical network communications system of the invention The system is constituted by one or more transmitter terminals TX connected to one or more receiver terminals RX via an optical network Z. In the general case, the transmitter terminal TX receives n input signals in electrical or optical form By way of non-limiting example, the figure illustrates the case where n 4.The input signals Ea-Ed are n synchronous signals th at are amplitude modulated and that represent binary data contained in successive bit times of duration T These input signals are to be transmitted on n time channels of the optical network, in the form of packets in time-division multiplex, each of which packets contains a predetermined number of information bits from one of the input signals For this purpose, the n input signals Ea-Ed are received by respective ones of n packet-forming circuits PF whose outlets deliver n optical signals Sa-Sd organized in packets The signals Sa-Sd are then time-division multiplexed by a circuit for time-division multiplexing packets TDM The resulting time-division multiplex signal Sx is then delivered to the network Z via a synchronization and re-shaping circuit SYNC. The packet-forming circuits PF and the synchronization circuit SYNC are controlled by respective selection signals SELi and a clock signal CK, these signals being delivered by an electronic control unit TC for controlling the transmitter terminal. The output signal S x of the transmitter terminal TX is transmitted via the network Z and it becomes an input signal Sy for the receiver terminal RX A coupler k receives the input signal Sy and takes therefrom a portion intended for an electronic control unit RC for controlling the receiver terminal, and another portion intended for a circuit for time-division demultiplexing packets TDD. The demultiplexer TDD performs serial-to-parallel conversion and delivers n demultiplexed optical signals S a-S d corresponding to respective ones of the n transmission channels The signals S a-S d are injected into respective ones of n packet decompression circuits PD which deliver deconcatenated and decompressed optical signals Ra-Rd to optical-to-electrical conversion and resynchronization circuits OE The circuits OE deliver electrical reception signals R a-R d. By taking a portion from the input signal Sy, the electronic control unit RC recovers the clock therefrom and generates an electric al control signal CT for controlling the time-division demultiplexer TDD electrical selection signals SEL i serving to control the packet decompression circuits PD and an electrical synchronization signal CK which controls the circuits OE. A more detailed description follows of the design and operation of the various elements of the communications system. FIG 2 is a diagram showing a concatenation circuit MCi of the invention making it possible to implement packet-forming circuits PF By way of illustration, FIG 2 corresponds to the case when binary data items or binary data blocks contained in an input signal Ei are grouped together in groups of four. The circuit includes a set 1 of light sources L 1 - L 4 capable of generating carrier waves of different wavelengths 1-4 These sources are connected to a first modulation circuit 2 controlled by an electrical selection signal SELi which defines time windows of width w and of period T delimiting the bits or the blocks of bits of the input sign al Ei that are to be concatenated. The modulator 2 delivers optical selection signals SC 1 - SC 4 to a second modulation circuit 3 controlled by the input signal Ei. The circuit 3 delivers converted input signals E 1 - E 4 which are then delayed by a delay circuit 4 to deliver corresponding delayed signals Er 1 - Er 4 to a combiner 5 The delays are such that any two consecutive delayed signals are offset in time by the duration w of the time windows For this purpose, the delay circuit 4 comprises, for example, delay lines d 2 d 3 d 4 creating respective delays T w, 2 T w , 3 T w intended for respective ones of the converted input signals E 2 E 3 E 4 A first inlet of the combiner 5 then receives E 1 directly, while its other inlets receive E 2 E 3 and E 4 via the respective delay lines d 2 d 3 and d 4.The combiner 5 is preferably an optical multiplexer tuned to the wavelengths 1-4 so as to deliver the multiplex signal Si constituted by the combination of the delayed signals Er 1 - Er 4 almost without loss. In the general case in which g bits or blocks of bits are to be concatenated, g optical sources having different wavelengths are provided for forming g converted input signals E 1 - Eg, and a delay circuit 4 is provided for applying the delays T w, 2 T w g 1 T w to respective ones of the converted input signals E 2 - Eg A multiplex signal Si is then obtained containing groups of g concatenated bits or of g concatenated blocks of bits, of width g w with a period g T. Operation of the circuit shown in FIG 2 is described below more precisely with reference to the timing diagrams a to h in FIG 3.In the general case, the input signal Ei is an amplitude-modulated synchronous optical or electrical signal Successive time windows of width w, and of period T, define the payload portions of the signals, i e the binary information bits, samples of bits, or blocks of bits , that are to be concatenated Provided that T is not less than 2 w, the circuit makes it possible to group together a number g lying in the range 2 to T w of bits or samples or blocks of bits In the example shown, g 4 and T w 5.The timing diagram a shows an example of how the amplitude of the input signal Ei varies over time In this example, the signal includes blocks of bits P 1 P 2 Pg The timing diagram b shows the selection signal SELi that is to be applied to the modulator 2 i e pulses of width w, of period T, and that cover the blocks P 1 P 2 Pg, thus forming the windows V 1 V 2 Vg. The converted input signals E 2 - Eg appear in the timing diagram c in which only the envelopes have been shown. The delayed signals Er 1 - Er 4 appear respectively in the timing diagrams c to f The multiplexed signal Si resulting from them being combined is shown by the timing diagram g. The timing diagram h shows the selection signal SEL i 1 that must then be provided to retain the payload concatenated groups only The selection signal SEL i 1 is made up of pulses of width g w with a period g T and that cover the success ive blocks of bits P 1 P 2 Pg. FIG 4 shows a first preferred embodiment MC 1 of the concatenation circuit MCi, when the input signal Ei is an electrical signal E 1.The circuit includes a set 11 of laser sources modulated by a selection signal SEL 1 so as to deliver the optical selection signals SC 1 - SC 4 to a wavelength-division multiplexer 6 whose outlet is connected to an optical gate 7 controlled by the electrical input signal E 1 In the general case, the multiplexer 6 can receive g optical selection signals at its inlets, and, in FIG 4, g 4 has been chosen by way of non-limiting example. The optical gate 7 delivers combined converted input signals E 2 - E 4 The circuit includes a three-port circulator A first port receives the converted input signals E 2 - E 4 a second port is connected to a delay circuit 4 made up of filters F 1 F 2 F 3 F 4 connected in cascade via delay lines d, and a third port delivers the multiplex signal S 1.The filters F 1 - F 4 are stop filters tuned to reflect respective ones of the wavelengths 1-4 To take into account the go-and-return path lengths of the waves, each of the delay lines d is dimensioned to create a delay equal to T w 2.The circuit shown in FIG 4 operates in the same way as the circuit shown in FIG 2 except that the converted input signals are firstly combined before they are delayed, by using the differences in their wavelengths With the filters F 1 - F 4 being stop filters set to respective ones of the wavelengths 1-4, and each of the delay lines being dimensioned to create a delay equal to T w 2, the delay circuit reflects the delayed signals Er 1 - Er 4 so that any two consecutive delayed signals are offset in time by the duration w, as shown in the timing diagrams c to f of FIG 3pared with the FIG 2 embodiment, in which the modulator 3 is made up of a plurality of optical gates connected to the delay line 4 the embodiment shown in FIG 4 offers the advantage of being less costly because only one gate 7 is necessary for the carrier waves to be modulated by the input signals However, adjusting the delays d is more difficult to achieve. FIG 5 shows another embodiment MC 2 of the concatenation circuit MCi This embodiment is suitable when the input signal Ei is an optical signal E 2 It includes a four-port circulator 10 A first port receives the input signal E 2 a second port is connected to a semiconductor optical amplifier 9 a third port is connected to a delay circuit 4 made up of filters F 1 F 2 F 3 F 4 connected in cascade via delay lines d , and a fourth port delivers the multiplex signal S 2.The amplifier 9 includes a first port connected to the second port of the circulator 10 and a second port opposite from the first port and connected to the outlet of a multiplexer 6.As in the preceding example, the multiplexer 6 receives the optical selection signals SC 1 - SC 4 delivered by respective ones of four light sources 11 suitable for generating carrier waves that have different wavelengths 1- 4 and that are modulated by a selection signal SEL 2.In operation, the selection signal SEL 2 modulates the sources 11 which deliver the optical selection signals SC 1 - SC 4 carried by respective ones of the wavelengths 1- 4 and of amplitude that reproduces the amplitude of the selection signal SEL 2.The optical selection signals SC 1 - SC 4 are combined by the multiplexer 6 and are then injected into the amplifier 9 via the second port thereof Via its first port, the amplifier 9 receives the optical input signal E 2 delivered by the second port of the circulator 10 The signal E 2 is thus injected in the opposite direction Since the amplifier medium is saturable, the gain applied to the signals SC 1 - SC 4 is modulated by the amplitude of the signal E 2 The first port of the amplifier 9 then delivers converted input signals E 1 - E 4 carried by respective ones of the wavelengths 1- 4 to the second port of the circulator 10.The converted input signals E 1 - E 4 are applied to the delay circuit 4 via the third port of the circulator 10 As in the preceding embodiment, with the filters F 1 - F 4 being stop filters tuned to reflect respective ones of the wavelengths 1- 4, and with each of the delay lines d being dimensioned to create a delay equal to T w 2, the delay circuit reflects the delayed signals E rl-E r 4 so that any two consecutive delayed signals are offset in time by the duration w, as shown in the timing diagrams c to f in FIG 3.A first variant embodiment consists in coupling the outlet of the multiplexer 6 directly to the circulator 10 and in placing an amplifier between each source of the set 11 and a corresponding inlet of the multiplexer This variant offers the advantage that the signal-to-noise ratio is independent of the number of sources, thereby making it possible to increase said number. Another variant is shown in FIG 7 In this variant, and as above, the outlet of the multiplexer 6 is coupled directly to the circulator 10 A first source is connected to a corresp onding inlet of the multiplexer via an amplifier 9 a while the other sources are connected to respective ones of the other inlets of the multiplexer via amplifiers 9 b 9 c 9 d and via delay lines d 2 d 3 d 4 To take into account the go-and-return path lengths of the waves, the delay lines d 2 d 3 and d 4 are dimensioned to create delays respectively equal to T w 2, T w, and 3 T w 2pared with the preceding variant, this configuration offers the advantage of making it easier to adjust the delays, and of avoiding constraints on the quality of the stop filters. The concatenation circuit of the invention may advantageously be used to constitute a bit time compression and packet-forming circuit by making provision to connect a plurality of such circuits in cascade To illustrate this possibility, in particular as applied to a packet optical transmission system, a description follows of the case when the FIG 4 circuit is connected in cascade with the FIG 5 circuit, with reference to the timing diagrams in FIGS 6A and 6B. One of the input signals Ea-Ed of the transmitter terminal TX then constitutes the electrical input signal E 1 of the FIG 4 circuit The timing diagram a of FIG 6A shows an example of how the amplitude of the signal Ea varies over time Said amplitude is modulated between high levels and low levels that represent binary data B 1 B 2 B 12 contained in successive bit times of duration T In this example, the signal is of the NRZ type. To perform time-division multiplexing on packets in real time, it is necessary firstly to compress the bit time of the signal in a ratio n not less than the number of channels of the time-division multiplex. To perform such compression, the selection signal SEL 1 acts as a sampling clock signal made up of pulses of frequency 1 T, of constant amplitude, of width w not more than T n, and set substantially to the middles of the bit times of the signal Ea The signal SEL 1 is shown in the timing diagram b of FIG 6A, for the case when w T n, with n 4.Modulating g1 sources 11 by the signal SEL 1 delivers g1 optical sampling signals SC 1 - SC 4 which, once they have been combined by the multiplexer 6 are modulated by the electrical input signal E 1 which delivers g1 converted input signals E 1 - E 4 to the circulator 8 as shown in the timing diagram c of FIG 6 A The delay circuit 4 reflects the delayed signals Er 1 - Er 4 which are shown in the timing diagrams c to f , in the particular case when g1 4 The combined signals constitute the output multiplex signal S 1 of the circuit shown in FIG 4.The signal S 1 is then used as the optical input signal E 2 of the FIG 5 circuit The selection signal SEL 2 modulating g2 sources 11 is shown in the timing diagram g of FIG 6 A This signal is made up of pulses of width g1 w, with a period g1 T, the pulses forming the time-windows of the signal E 2 Naturally, the signal SEL 2 is set so that each of the pulses that make it up covers g1 successive samples of the input signal Ea. The circuit shown in FIG 5 generates g2 second converted input signals E 1 - E 4 shown in the timing diagram h The signals E 1 - E 4 represent the concatenated binary information of the electrical input signal E 1 of the FIG 4 circuit Hence, there are blocks P 1 P 2 P 3 each of which is made up of g1 binary data items, the blocks being of width g1 w with a period g1 T. The block envelopes P 3 - P 8 making up the signals E 1 - E 4 are shown in the timing diagram a of FIG 6 B The delay circuit 4 delivers the second delayed signals E r 1 - E r 4 whose envelopes are shown in respective ones of the timing diagrams a to d , in the particular case when g2 4 The resulting multiplex signal S 2 is shown in the timing diagram e , in which the blocks P 1 - P 8 can be seen concatenated into groups of 4 In the general case, each of the groups includes g2 blocks, the groups are of width g2 g1 w, with a period g1 g2 T. Thus, by coupling a plurality of concatenation circuits in cascade, it is possible to constitute a pack et-forming circuit for forming packets grouping together any number of binary data items This possibility is shown in FIG 8 which shows a packet-forming circuit PF made up of concatenation circuits MC 1 MC 2 MCi, MCp coupled in cascade and controlled by respective ones of the selection signals SEL 1 SEL 2 SELi, SELp chosen to form groups respectively of g1, of g2, of g1, and of gp The last concatenation stage MCp is connected to an output modulator MS controlled by the selection signal SEL p 1 serving to retain the payload concatenated groups only The packet-forming circuit PF may advantageously be used in the transmitter terminal TX of the above-described transmission system. FIG 9 shows an embodiment for putting two concatenation circuits in cascade The cascade circuit is made up of two FIG 5 circuits, and it has a single six-port circulator 12 making it possible to couple the optical input signal Ei to the inlet of a first stage MCi, and to couple the outlet of said first stage to th e inlet of the following stage MC i 1.FIG 10 shows an embodiment of a packet time-division multiplexer TDM that can be used in the transmitter terminal TX The circuit is constituted merely by a delay circuit connected to the inlets of an n-to-1 coupler 13 The delay circuit is made up of delay lines D, 2 D, 3 D so as to apply respective delays 0 U, 2 U, 3 U nU to the n output signals Sa-Sd of the packet-forming circuits PF, where U is the duration of each packet formed by the circuits PF. FIG 11 shows an embodiment of the packet time-division demultiplexer TDD that can be used in the receiver terminal RX This circuit includes a 1-to-n coupler 14 receiving the signal Sy output by the network Z The n outlets of the coupler 14 are connected to a modulator 15 via a delay circuit 3 D, 2 D, D as defined above The modulator 15 is controlled by a control signal CT constituted by pulses of width equal to the width U of the packets and of period nU The modulator 15 delivers at its outlets the comp ressed signals S a-S d corresponding to respective ones of the various channels of the transmitted time-division multiplex. FIG 12 shows an embodiment of a deconcatenation circuit making it possible to constitute a packet decompression circuit PD for the receiver terminal RX. This circuit includes a set 16 of g laser sources modulated by a selection signal SEL A first source is connected to a corresponding inlet of the multiplexer 17 while the other sources are connected to respective ones of the other inlets of a multiplexer 17 via delay lines d 1 2 d 1 3 d 1 so as to deliver optical block-selection signals SB 1 - SB 4 to the inlets of the multiplexer 17.It includes a four-port circulator 19 A first port receives one of the compressed signals S a, a second port is connected to a semiconductor optical amplifier 18 a third port is connected to a delay circuit 20 made up of filters F 1 F 2 F 3 F 4 connected in cascade via delay lines D 2 and a fourth port delivers a deconcatenated signal S p. The amplifier 18 has a first port connected to the second port of the circulator 19 and a second port opposite from the first port and connected to the outlet of the multiplexer 17.Operation of the circuit shown in FIG 12 can be described by means of the timing diagrams of FIG 13 The timing diagram a shows one of the signals S a which is made up of packets Pa 1 Pa 2 of width U and of period Ta Each packet Pa 1 P 2 is made up of data blocks B 1 - B 4 B 5 - B 8 that are to be deconcatenated For this purpose, it is necessary merely to apply the selection signal SEL shown in the timing diagram b This signal is made up of pulses whose width U g is equal to that of the blocks B 1 - B 8 and whose period is equal to the period Ta of the packets Since the delay lines d 1 2 d 1 3 d 1 are dimensioned to apply delays that are multiples of the block width, optical block-selection signals SB 1 - SB 4 not shown are obtained that cover respectively the blocks B 1 and B 5 B 2 and B 6 B 3 and B 7 and B 4 and B 8 The optical block-selection signals SB 1 - SB 4 are modulated by the signal S a in the amplifier 18 which delivers converted block signals S 1 - S 4 to the circulator 19 which signals are carried by respective ones of the wavelengths 1-4 The envelopes of the signals S 1 - S 4 are shown respectively in the timing diagrams c to f. With the filters F 1 - F 4 being stop filters tuned to reflect respective ones of the wavelengths 1-4, and with each of the delay lines D 2 being dimensioned to create a delay equal to Ta-U 2 g , the delay circuit 20 reflects the deconcatenated signal S p This signal S p is thus obtained by combining and delaying the converted block signals S 1 - S 4 so as to form delayed blocks of period Ta g , as shown in the timing diagram g. A first variant embodiment consists in coupling the outlet of the multiplexer 17 directly to the circulator 19 and in placing an amplifier between the first source and the first inlet of the multiplexer, and between each delay li ne d 1 2 d 1 3 d 1 and a corresponding inlet of the multiplexer This variant offers the advantage that the signal-to-noise ratio is independent of the number of sources, thereby making it possible to increase said number. Another variant analogous to the embodiment shown in FIG 7 consists in connecting the inlets of the multiplexer to the amplifiers via delay lines replacing the delay circuit 20.This configuration offers the advantage of facilitating adjustment of the delays, and it avoids constraints on the quality of the stop filters of the delay circuit. To implement the packet decompression circuit PD, it is possible to put in cascade a plurality of deconcatenation circuits as described above, thereby making it possible to re-establish the bit frequency of each channel to a value equal to the bit frequency of the input signals of the transmitter terminal A final, pulse-spreading stage restores NRZ modulation. FIG 14 shows an embodiment of the spreader stage The circuit includes a modu lator MZ receiving firstly the outlet signal S 1 from the last of the deconcatenation circuits, and secondly a combination of carrier waves having different wavelengths e-h delivered by laser oscillators Le-Lh via a multiplexer M. A circulator C has a first port connected to the outlet of the modulator MZ, a second port connected to a delay circuit, and a third port delivering a decompressed signal Ra The delay circuit may be made up of stop filters Fe-Fh connected in cascade via delay lines D 3 The filters Fe-Fh are tuned to reflect respective ones of the wavelengths e-h To take into account the go and return path lengths of the waves, each of the delay lines D 3 is dimensioned to create a delay substantially equal to w 2.The signal Ra is applied to an optical-to-electrical converter OE constituted, for example, by a photodiode, so as to deliver the electrical output signal R a. The modulator MZ may be of interferometer structure, e g of the Mach-Zehnder type, organized to form construc tive interference when the power level of the input signal S 1 is high. In operation, the modulator MZ delivers auxiliary signals S-Sh carried by respective ones of the wavelengths e-h, each signal reproducing the modulation of the signal S 1 as shown in the timing diagram a of FIG 15 The auxiliary signals Se-Sh are reflected and delayed by the delay circuit, and they are then fed back into the circulator C The corresponding delayed signals Re-Rh are shown respectively in the timing diagrams a to d of FIG 15 The circulator C then delivers a combination of these signals that constitutes the decompressed signal Ra shown in the timing diagram e. Method and apparatus for transcoding binary information for time domain multiplex transmission EP 0119140 A1.The invention relates to the transcoding of binary informations Successive binary data forming each information to be transmitted are transcoded four by four according to a ternary code wherein to each of the possible groups of four binary va lues corresponds a combination of four ternary values which is selected among two different combinations assigned to the group considered, one of the two combinations corresponding to the addition of a supplementary indication predetermined with respect to the other one The coder device 1 and the decoder device 3 comprise each a transcoder 6, 11 organized in association with a read-only memory The invention relates to wire telecommunication timedivision networks and particularly to multiservice telephone exchangers. 1. 2. 10 .1 Proc d de transcodage d informations binaires pour transmission multiplexe temporelle permettant la reconstitution de ces informations binaires apr s transmission, caract ris en ce que les donn es binaires successives constituant chaque information sont transcod es quatre par quatre, selon un code ternaire dans lequel chacun des groupements possibles de quatre valeurs binaires a pour correspondant une combinaisons de quatre valeurs ternaires qui est choisie parmi deux combinaisons diff rentes affect es au groupement consid r , l une des deux combinaisons affect es un m me groupement correspondant l adjonction d une indication suppl mentaire pr d termin e par rapport l autre, de mani re a conserver un m me d bit d informations qu il y est ou non transmission d indications suppl mentaires 1 A method for transcoding binary data for time-division multiplex transmission for reconstructing these binary information after transmission, characterized in that the successive bina ry data constituting each information are transcoded four by four using a ternary code in which each of the possible groups of four binary values corresponds to a combination of four ternary values which is selected from two different combinations assigned to the considered group, one of the two combinations assigned to the same group corresponding to the addition of a predetermined additional indication over the other, so as to maintain the same flow rate information or that there is no transmission of additional information.2 Proc d de transcodage selon la revendication 1, pour transmission par l interm diaire de voies temporelles rep r es par leur positionnement vis - - vis d une indication de verrouillage identiquement positionn e au cours des trames successives de transmission, caract ris en ce que l indication de verrouillage est traduite par le choix de la combinaison de quatre valeurs ternaires qui correspond l adjonction d une indication suppl mentaire pour le groupement de quat re valeurs binaires coder simultan ment avec une telle indication de verrouillage 2 A transcoding method according to claim 1, for transmission through time slots identified by their position vis - - vis positioning a lock indication identically positioned in successive transmission frames, characterized in that the lock indication is translated by the choice of the combination of four ternary values which corresponds to the addition of an additional indication for the group of four binary values to be encoded simultaneously with such an indication of locking.3 Proc d de transcodage selon la revendication 1, caract ris en ce que les combinaisons de quatre valeurs qui correspondent la transmission d un groupement sans adjonction d indication suppl mentaire sont de poids plus faible que les combinaisons qui correspondent la transmission d un groupement avec adjonction d une indication suppl mentaire 3 A method of transcoding according to claim 1, characterized in that the four combinations of values that correspond to the transmission of a group without addition of additional indication are of lower weight than the combinations corresponding to the transmission of a group with the addition of an additional indication 4 Proc d de transcodage selon la revendication 3, caract ris en ce que les combinaisons qui correspondent la transmission d un groupement sans adjonction d indication suppl mentaire sont de poids nul 4 A transcoding method according to claim 3, characterized in that the combinations corresponding to the transmission of a group without addition of additional indication are zero weight.5 Proc d de transcodage selon la revendication 3, caract ris en ce que les combinaisons qui correspondent la transmission d un groupement avec adjonction d une indication suppl mentaire ont un poids sup rieur celui qui peut tre obtenu par l association de quatre valeurs successives prises dans deux combinaisons successives correspondant la transmission de deux groupements sans adjonction d indication suppl mentaire 5 A transcoding method according to claim 3, characterized in that the combinations corresponding to the transmission of a group with addition of an additional indication have a weight greater than that which can be obtained by the association of four successive values taken in two successive combinations corresponding to the transmission of two groups without addition of additional indication.6 Dispositif codeur pour la mise en oeuvre du proc d selon au moins l une des revendications pr c dentes, caract ris en ce qu il comporte 6 An encoder device for carrying out the method according to at least one of the preceding claims, characterized in that it comprises.- un transcodeur binaire-binaire 6 fournissant une association diff rente de huit donn es binaires pour chacun des groupements possibles de quatre valeurs binaires DB ou SI affect ou non d une indication suppl mentaire - A binary-binary transcoder 6 providing a different combination of eight binary data for each of the possible groups of four binary values DB or SI affected or not an additional indication.- un convertisseur binaire-ternaire 7 scindant chaque association de huit donn es binaires issus du transcodeur 6 en deux groupes de quatre donn es, de mani re transmettre sur une liaison de transmission 2 un signal r sultant obtenu en prenant en compte simultan ment une donn e binaire de chaque groupe de quatre - A binary-to-ternary converter 7 dividing each association of eight binary data from the transcoder 6 into two groups of four data, in order to transmit on a transmission link 2 a resultant signal obtained by simultaneously taking into account a binary data of each group of four.7 Dispositif codeur selon la revendication 6, caract ris en ce que le transcodeur binaire-binaire 6 comporte essentiellement une m moire lecture seule 14 contenant de mani re individuellement adressable les diff rentes associations de huit donn es binaires mises en oeuvre dans le proc d , l adressage tant assur par l interm diaire d une entr e d indication suppl mentaire VT et de quatre entr es de donn es binaires d information DB et ou de signalisation SI , sous le contr le d une horloge H 4 7 An encoder device according to claim 6, characterized in that the binary-binary transcoder 6 essentially comprises a read only memory 14 of individually addressable manner the different associations containing eight binary data implemented in the method, the addressing being ensured via an additional indication input VT and four binary data inputs information DB and or signaling IS , under the control of a clock H 4.8 Dispositif codeur selon la revendication 6, caract ris en ce que le convertisseur binaire-ternaire 7 est constitu de deux registres entr es parall les et sortie s rie reli s en parall le chacun a quatre sorties de donn es binaires diff rentes du transcodeur binaire-binaire 6 de mani re appliquer simultan ment chacun une borne du primaire d un transformateur 4 d en tr e de liaison de transmission 2 chaque temps d une horloge H , un signal binaire de niveau lectrique correspondant la valeur de l une des donn es qu ils ont simultan ment re ues 8 An encoder device according to claim 6, characterized in that the ternary-binary converter 7 consists of two registers with parallel inputs and serial output connected in parallel each with four outputs of different binary data of the binary-binary transcoder 6 so as to simultaneously apply each to a terminal of the primary of a transformer 4 transmission link inlet 2 at each time of a clock H , a binary signal corresponding to the power level value of one of the data they received simultaneously.9 Dispositif d codeur pour la mise en oeuvre du proc d selon au moins l une des revendications pr c dentes, caract ris en ce qu il comporte 9 A decoding device for carrying out the method according to at least one of the preceding claims, characterized in that it comprises.- un circuit de reconstitution d horloge 9 en sortie d une liaison de transmission 2 bifilaire, - A clock recovery circuit 9 the output of a transmission link 2 two-wire.- un convertisseur ternaire-binaire 8 reli en sortie de la liaison de transmission 2 en parall le avec le circuit de reconstitution d horloge 9 pour relever le niveau lectrique de chaque fil au rythme des signaux fournis par ce circuit d horloge 9 de mani re fournir par groupes de quatre donn es les donn es correspondant aux niveaux lectriques relev s en succession sur chaque fil, - A ternary-binary converter 8 connected to the output of the transmission link 2 in parallel with the clock recovery circuit 9 to raise the electric level of each wire at the rhythm of the signals supplied by this clock circuit 9 so as to provide groups of four data the data corresponding to the electric levels recorded successively on each wire.- un transcodeur binaire-binaire 11 recevant simultan ment les donn es manant du convertisseur ternaire-binaire 8 en deux groupes de quatre donn es pour en d duire soit un groupement de quatre valeurs binaires d information ou signalisation DB, SI et ventuellement une indication suppl mentaire VT , soit une indication d anormalit CX - A binary-binary transcoder 11 receiving simultaneously the data from the ternary-binary converter 8 into two groups of four data in order to deduce whether a group of four binary information or signaling values DB, SI and possibly an additional indication VT , an indication of abnormality CX.- un circuit de contr le 10 reli en sortie du transcodeur binaire-binaire 11 et du circuit de reconstitution d horloge 9 pour contr ler la reconstitution des informations DB et de signalisation SI par ce transcodeur 11 - A control circuit 10 connected to the output of the binary-binary transcoder 11 and the clock recovery circuit 9 for controlling the recovery of information DB and signal SI by the transcoder 11.10 Dispositif d codeur selon la revendication 9, caract ris en ce que le convertisseur ternai re-binaire 8 est compos de deux unit s de registres 24, 25 respectivement ins r es entre une borne du secondaire d un transformateur de sortie 5 de liaison de transmission 2 et le transcodeur binaire-binaire 11 de mani re fournir chacun quatre par quatre les donn es qu ils re oivent un rythme donn par le circuit de reconstitution d horloge 9 10 decoding device according to claim 9, characterized in that the ternary-binary converter 8 is composed of two registers of units 24, 25 respectively inserted between one terminal of the secondary of an output transformer 5 transmission link 2 and the binary-binary transcoder 11 so as to provide each four by four the data which they receive at a rhythm given by the clock recovery circuit 9.11 Dispositif d codeur selon la revendication 9, caract ris en ce que le transcodeur binaire-binaire 11 comporte une m moire lecture seule 31 dont les entr es d adressage sont reli es en sortie d un d codeur 29 huit entr es reli es aux sorties des unit s de reg istres 24, 25 , de mani re fournir pour chaque adressage soit un groupement de quatre valeurs binaires DB ou SI et ventuellement une indication suppl mentaire VT soit une indication d anormalit CX 11 decoding device according to claim 9, characterized in that the binary-binary transcoder 11 comprises a read only memory 31 whose address inputs are connected to the output of a decoder 29 having eight inputs connected to the outputs of the registers of units 24, 25 so as to supply for each address either a group of four binary values DB or SI and possibly an additional indication VT is an indication of abnormality CX.12 Dispositif d codeur selon la revendication 9, caract ris en ce que le circuit de contr le 10 comporte un automate de contr le 33 et un compteur-d compteur 34 , l automate de contr le recevant une information de verrouillage interne TO fournie par le compteur-d compteur 34 et l indication suppl mentaire VT fournie par le transcodeur binaire-binaire 11 , le compteur-d compte ur 34 recevant des signaux de repositionnement PR r ception d une indication suppl mentaire et les signaux d horloge HR issus du circuit de reconstitution 9 sur son entr e d horloge 12 decoding device according to claim 9, characterized in that the control circuit 10 comprises a control automaton 33 and a reversible counter 34 , the recording controller receiving an internal locking information TO supplied by the up-down counter 34 and the additional indication VT provided by the binary-binary transcoder 11 , the up-down counter 34 receiving the reset signals PR on reception of an indication and the additional clock signals HR from the recovery circuit 9 on its clock input. La pr sente invention a pour objets un proc d et des dispositifs de transcodage d informations binaires pour transmission multiplexe temporelle The present invention has for object a method and device for transcoding binary data for time-division multiplex transmission. De mani re classique voqu e notamment dans le ch apitre 2 4 1 R seau Num rique int gr du tome 1 de l ouvrage intitul La commutation lectronique publi en 1980 dans la Collection Technique et Scientifique des T l communications plac e sous les auspices du Centre National d tudes des T l communications et dit e par les ditions Eyrolles Paris, les informations binaires transmises par des liaisons de transmission multiplexe dans un r seau num rique int gr sont classiquement transcod es pour les quipements qui les mettent de mani re inclure des indications d horloge et de synchronisation permettant aux quipements qui les re oivent de les reconstituer par transcodage inverse Conventionally raised, in particular in Chapter 2 4 1 Integrated Digital Network in Volume 1 of the book entitled Electronic switching published in 1980 in the Technical and Scientific Telecommunications Collection under the auspices of the National Centre for Studies Telecommunications and edited by Eyrolles in Paris, the binary information transmitted by multiplex tra nsmission links in an integrated digital network are typically transcoded for equipment that issue to include clock and synchronization information enabling equipment who receive reconstruct the reverse transcoding. En effet, classiquement on cherche viter la mise en place de liaisons sp cifiques de transmission de signaux d horloge et de synchronisation d s que les longueurs de transmission ne sont plus n gligeables Indeed, traditionally sought to avoid the introduction of specific transmission of clock signals and synchronization connections as soon as the transmission lengths are no longer negligible Simultan ment on s efforce de comprimer la bande passante hors-tout des signaux transmis afin de favoriser une transmission et par cons quent une restitution correcte des informations At the same time we try to compress the bandwidth Overall transmitted signals to promote transmission and therefore a correct return of information On t che aussi de permettre une d tection intrins que des erreurs intervenant au niveau des transmissions Also one task to allow a detection of intervening intrinsic errors in the transmissions Souvent on cherche aussi supprimer la composante continue du spectre des signaux transmis pour pouvoir isoler galvani - quement les liaisons de transmission par rapport aux quipements qu elles relient Often it also seeks to remove the DC component of the spectrum of the transmitted signals to be isolated galvanically transmission links for the equipment they connect. Ceci conduit rechercher des codes de transmission pr sentant le meilleur compromis possible en fonction des exigences, tel le code HDB3 classiquement utilis pour les transmissions multiplexes temporelles externes d informations initialement cod es en code binaire de type NRZ vers et partir des terminaux de jonction externes de bon nombre de r seaux de commutation temporelle This led to a search for transmission code with the best possible compromise based on the requirements, such as HDB3 co de conventionally used for external time-division multiplex transmission of information originally encoded in binary NRZ to and from junction terminals many of external time switching networks. Une exigence suppl mentaire classiquement non obtenue avec les transmissions multiplexes temporelles usuelles est que la totalit du d bit nominal d une liaison soit affect e la transmission des informations binaires re ues par l quipement qui les met An additional requirement conventionally not obtained with the conventional time-division multiplex transmission is that the whole of the nominal flow of a link is assigned to the transmission of binary information received by the equipment sending them. Ainsi par exemple la trame des transmissions multiplexes MIC primaires ne permet d affecter que trente des trente deux voies la transmission des informations binaires pour les besoins des utilisateurs, puisque les voies restantes servent la signalisation et la synchronisation For example, the frame of primary PCM multiplex transmissions to assign thirty of the thirty two channels for the transmission of binary information to the needs of users, since the remaining channels are used for signaling and synchronization Si ceci est un inconv nient acceptable lorsque le nombre de voies temporelles inaccessibles aux utilisateurs est faible par rapport au nombre de voies disponibles, il n en est plus de m me dans le cas contraire If this is an acceptable disadvantage if the number of time slots inaccessible to users is small compared to the number of available channels, it is no longer the same otherwise Or il est parfois n cessaire de disposer de liaisons temporelles ne comportant qu un tr s petit nombre de voies, par exemple dans les centraux priv s temporels de type multiservices comportant des quipements lents notamment distants But sometimes it is necessary to have temporal links having only a very small number of routes, for example in the time-PBX multiservice type comprising notabl y slow remote equipment. La pr sente invention propose donc un proc d de transcodage d informations binaires pour transmission multiplexe temporelle qui permette d une part la reconstitution des informations binaires apr s transmission, d autre part la transmission d indications suppl mentaires et en particulier d indications de verrouillage de trame, tout en conservant un m me d bit d informations binaires en pr sence ou en l absence d indications suppl mentaires The present invention therefore provides a binary information transcoding method for time-division multiplex transmission that allows a share reconstitution after transmission of binary information, on the other hand the transmission of additional information and in particular lock indications frame, while maintaining the same information bit rate in the presence or in the absence of additional information. La pr sente invention propose galement un dispositif de transcodage ou codeur et un dispositif de transcodage inverse ou d codeur, pour la mise en oeuvre du proc d selon l invention The present invention also provides a transcoding device or encoder and an inverse transcoding device or decoder for carrying out the method according to the invention. Selon une caract ristique du proc d de transcodage selon l invention la donn es binaires successives constituant chaque information sont transcod es quatre par quatre, selon un code ternaire dans lequel chacun des groupements possibles de quatre valeurs binaires a pour correspondant une combinaison de quatre valeurs ternaires qui est choisie parmi deux combinaisons diff rentes affect es au groupement consid r , l une des deux combinaisons affect es un m me groupement correspondant l adjonction d une indication suppl mentaire pr d termin e par rapport l autre combinaison, de mani re conserver un m me d bit d informations binaires qu il y est ou non transmission d indications suppl mentaires According to a feature of the transcoding method according to the inventi on the successive binary data constituting each information are transcoded four by four using a ternary code in which each of the possible groups of four binary values corresponds to a combination of four ternary values which is selected from two different combinations assigned to the considered group, one of the two combinations assigned to the same group corresponding to the addition of a predetermined additional indication over the other combination, so as to retain the same information bit rate there is or is not transmitting additional indications. Selon une autre caract ristique de l invention le dispositif codeur comporte According to another feature of the invention the encoder means comprises.- un transcodeur binaire-binaire fournissant une association diff rente de huit donn es binaires en deux groupes de quatre pour chacun des groupements possibles de quatre valeurs binaires affect ou non d une indication suppl mentaire - A binary-binary transcoder supplying a different combi nation of eight binary data into two groups of four for each of the possible groups of four binary values assigned or not an additional indication.- un convertisseur binaire-ternaire scindant chaque association de huit donn es binaires en deux groupes de quatre donn es de mani re transmettre sur une liaison de transmission un signal r sultant obtenu en prenant simultan ment en compte une donn e binaire de chaque groupe de quatre - A binary-ternary converter splitting each association of eight binary data into two groups of four data to be transmitted on a transmission link a resultant signal obtained by taking into account simultaneously a binary data item of each group of four. Selon une autre caract ristique de l invention le dispositif d codeur comprend According to another feature of the invention the decoder means comprises.- un circuit de reconstitution d horloge en sortie d une liaison de transmission bifilaire, - A clock recovery circuit at the output of a two-wire transmission link.- un convertisseur ternaire-binaire reli en sortie de liaison de transmission en parall le avec le circuit de reconstitution d horloge pour relever le niveau lectrique sur chaque fil au rythme des signaux fournis par ce circuit de reconstitution de mani re fournir par groupes - A ternary-binary converter connected transmission link in parallel with the output clock recovering circuit for raising the power level of each wire at the rhythm of the signals supplied by this circuit to provide reconstitution by groups de quatre donn es, les donn es correspondant aux niveaux lectriques relev s en succession sur chaque fil, of four data the data corresponding to the electric levels recorded successively on each wire.- un transcodeur binaire-binaire recevant simultan ment les donn es manant du convertisseur ternaire en deux groupes de quatre donn es pour en d duire soit un groupement de quatre valeurs binaires d information ou de signalisation et ventuellement une indication suppl mentaire , soit une indication d anormalit , - A binary-binary transcoder receiving simultaneously the data from the ternary converter into two groups of four data in order to deduce whether a group of four binary values or signaling information and possibly an additional indication, an indication of abnormality. un circuit de r cup ration d indication suppl mentaire reli en sortie du transcodeur binaire-binaire et du circuit de reconstitution d horloge pour contr ler la reconstitution des informations et des signalisations par le transcodeur a further indication of recovery circuit connected to the output of the binary-binary transcoder and clock recovery circuit for controlling the recovery of information and messages by the transcoder. L invention, ses caract ristiques et ses avantages sont pr cis s dans la description qui suit, en relation avec les figures ci-dessous r pertori es The invention, its features and its advantages are explained in the following description in conjunction with the following figures listed. La figure 1 pr sente un sch ma de principe, partiel, d une transmission multiplex temporelle permettant la mise en oeuvre du proc d de transcodage selon l invention 1 shows a block diagram, part of a time-division multiplex transmission for the implementation of the transcoding method according to the invention. La figure 2 pr sente le sch ma d un dispositif codeur selon l invention 2 shows the diagram of an encoder device according to the invention. La figure 3 pr sente le sch ma d un dispositif d codeur selon l invention Figure 3 shows the diagram of a decoding device according to the invention. La figure 4 pr sente un diagramme repr sentatif du fonctionnement d un dispositif d codeur selon l invention 4 shows a diagram representing the operation of a decoding device according to the invention. La transmission multiplexe temporelle partiellement repr sent e la figure 1 est par exemple destin e relier deux organes tels qu un coupleur d un r seau de commutation num rique un terminal desservant un ou plusieurs appareils metteurs et ou r cepteurs de donn es, ces divers l ments n tant pas repr sent s ici dans la mesure o ils n entrent pas dans le cadre de l invention The time-division multiplex transmission partially shown in Figure 1 is for example for connecting two members such as a coupler of a digital switching network to a terminal serving one or more transmitters and or data receivers, these elements n being shown here insofar as they do not fall within the scope of the invention. De mani re usuelle cette transmission multiplexe temporelle comporte un dispositif codeur d mission 1, recevant sous forme binaire des informations DB transmettre multiplex es dans le temps entre elles et ventuellement avec des signalisations SI galement sous forme binaire The usual way that time-division multiplex transmission comprises a transmission encoder device 1, receiving binarizing DB information to be transmitted multiplexed in time between them and possib ly with IF signals also in binary form L ensemble des donn es binaires composant ces informations et ces signalisations parviennent classiquement au rythme des signaux d une horloge H non figur e qui est affect e par exemple l organe auquel le dispositif codeur 1 est attribu Set of binary data comprising this information and these signals typically arrive at the timing of signals of a non figured H clock which is assigned for example to the body to which the encoder device 1 is assigned. Des indications suppl mentaires VT sont galement fournies sous contr le de l horloge H par exemple pour permettre la restitution des informations et des signalisations apr s transmission, ces indications suppl mentaires VT sont classiquement des verrouillages de trame, ou ventuellement des tiquettes signalant le d but et ventuellement la fin d une information ou signalisation sp cifique Further guidance VT may also be provided under control of the clock H for example to allow the restitution of the info rmation and signals after transmission, these additional directions VT are conventionally weft interlocks, or optionally labels indicating the start and possibly the end of specific information or signaling. Le dispositif codeur 1 tel que pr sent en figure 1, est reli une liaison de transmission 2 ici unidirectionnelle sur laquelle il met sous forme impulsionnelle, vers un d codeur de r ception 3 The encoder device 1 as presented in Figure 1, is connected to a transmission 2 by way link on which it transmits in pulse form, to a receiving decoder 3.Dans l exemple pr sent la liaison de transmission 2 est symbolis e par une classique liaison bifilaire laquelle le dispositif codeur 1 et le dispositif d codeur 3 sont reli s par l interm diaire de transformateurs d entr e 4 et de sortie 5 qui assurent d une part la transmission des impulsions du dispositif codeur la liaison et d autre part de cette liaison au dispositif d codeur In the example of the transmission link 2 is symbolized by a con ventional two-wire connection in which the encoder device 1 and decoding device 3 are connected via input transformers 4 and Release 5 which provide on the one hand transmission of pulses of the encoder device to the link and the other of the link to the decoder device. Bien entendu selon une pratique usuelle la liaison de transmission 2 peut tre associ e une liaison de transmission de sens inverse permettant des changes bidirectionnels simultan s, elle peut galement desservir un ou plusieurs dispositifs codeurs d mission fonctionnant alternativement en relation avec un ou plusieurs dispositifs d codeurs de r ception Of course according to a usual practice the transmission link 2 may be associated with an opposite direction of transmission link for simultaneous bidirectional exchanges, it can also serve one or more encoders emission devices operating alternately in connection with one or more decoding devices reception. Selon une technique usuelle, les signaux binaires constituant les in formations et signalisations transmettre sont transcod s au niveau du dispositif codeur 1 afin de satisfaire au mieux aux objectifs de transmission que l on s est fix et ils sont transcod s en sens inverse au niveau du dispositif d codeur 2 de mani re tre restitu s sous forme binaire pour les besoins de l exploitation According to a conventional technique, the binary signals constituting the information and messages to be transmitted is transcoded on the encoder device 1 in order to best meet the objectives of transmission that one is fixed and they are transcoded in the opposite direction at the 2 decoder device so as to be output in binary form for operational purposes. Selon un premier objectif, d j voqu plus haut, selon l invention on cherche transmettre simultan ment les donn es binaires constituant les informations DB, les signalisations SI, les signaux d horloge d mission H et les indications suppl mentaires VT According to a first objective, already mentioned above, the inventio n is sought to simultaneously transmit binary data constituting the DB information, IF signals, H transmit clock signals and additional guidance VT Ceci est obtenu au niveau du dispositif codeur 1 par un transcodeur binaire-binaire 6 associ un convertisseur binaire-ternaire 7 This is obtained at the encoder device 1 by a binary-binary transcoder 6 associated with a binary-ternary converter 7.Au niveau du dispositif d codeur 3, un transcodeur binaire-binaire 11 en s rie avec un convertisseur ternaire-binaire 8 en sortie de liaison de transmission 2 permet de reconstituer les informations DB et les signalisations SI Un circuit de reconstitution d horloge 9 plac en parall le avec le convertisseur ternaire-binaire 8 en sortie de liaison 2 fournit des signaux d horloge HR qui correspondent aux signaux de l horloge H ayant servi l mission par le dispositif codeur 1, il contr le le transcodeur binaire-binaire 11 The decoder device level 3, a binary-binary transcoder 11 in series with a ternar y-binary converter 8 2 transmission link output allows to reconstruct the DB information and the IF signals A clock recovery circuit 9 placed in parallel with the ternary-binary converter 8 by connecting two output provides HR clock signals corresponding to the H clock signals used for transmission by the encoder device 1, it controls the binary-binary transcoder 11.Un circuit de contr le 10 est galement plac en sortie du convertisseur ternaire-binaire 8, afin de contr ler et exploiter les indications suppl mentaires VT transmises, il re oit les signaux de temps provenant du circuit de reconstitution d horloge 9 A control circuit 10 is also placed at the output of the ternary-binary converter 8 in order to control and exploit the additional information transmitted VT, it receives time signals from the clock recovery circuit 9me on l a vu plus haut, on cherche r server la plus grande partie possible du canal de transmission que forme la liaison 2 pour les informations binaires DB transm ettre et ce quelle que soit la taille du canal As noted above, we try to book the largest possible part of the transmission channel that forms the connection 2 for binary information to be transmitted and DB regardless the size of the channel Ainsi dans le cas de transmissions multiplexes temporelles 2 incluses dans un syst me de commutation temporelle non figur comportant des canaux de diff rentes tailles allant par exemple de quatre cent vingt huit voies par trame on s efforce de r server le plus grand nombre de voies et d intervalles de temps de voie au trafic d informations binaires DB Thus in the case of time-division multiplex 2 transmissions included in a not shown time switching system with up channels of different sizes, for example, four to one hundred and twenty eight channels per frame we try to book as many channels and channel time intervals binary data traffic DB Ceci peut impliquer par exemple une transmission des signalisations sous forme de messages permettant de lib rer pour l usage g n ral les intervalles de temps d une voie pr vue pour les signalisations en l absence de telles signalisations This may involve, for example, transmission of signals in the form of messages for free for general use time slots of a channel provided for signaling in the absence of such signs. Selon l invention on regroupe les donn es binaires successives transmettre quatre par quatre, ce qui est g n ralement sans probl me car les informations binaires et les signalisations sont souvent compos es d octets ou de quartets ou de multiples de ces octets ou de ces quartets, comme cela est en particulier pour les signaux de parole cod s MIC ou les signalisations par quartet des syst mes de commutation temporelle MIC selon l avis G732 du CCITT According to the invention comprises the successive binary data to be transmitted four by four, which is usually no problem because the binary information and the signals are often composed of bytes or nibbles or multiples of these bytes or nibbles such as this is particularly the coded speech signals or PCM signals quartet by MIC temporal switching systems in the opinion CCITT G732.Chaque groupement de quatre donn es binaires successives regroup es est ensuite transcod selon un code ternaire dans lequel chacun des seize groupements possibles de quatre valeurs binaires a pour correspondant une combinaison de quatre valeurs ternaires qui est choisie parmi deux de trente-deux des quatre vingt et une combinaisons ternaires possibles Each group of four successive binary data is then transcoded grouped according to a ternary code in which each of the sixteen possible groups of four binary values corresponds to a combination of four ternary values which is selected from two of thirty-two of the twenty four and a combination possible ternary. Chaque groupement de quatre donn es binaires a donc pour correspondant deux combinaisons de quatre valeurs ternaires, l une des combinaisons est associ e l adjonction d une indication sup pl mentaire pr d termin e par rapport l autre Each group of four binary data thus corresponding to four combinations of two ternary values, one of the combinations is associated with the addition of a predetermined additional indication over the other. On peut ainsi transmettre par s lection d une combinaison ou l autre soit un groupement, soit ce groupement plus une indication suppl mentaire tout en utilisant dans chaque cas uniquement quatre valeurs ternaires, cette indication suppl mentaire VT est par exemple une indication de rep rage transmises en m me temps que les premi res donn es d un message ou que des donn es d informations DB transmettre Can thus be transmitted by selecting a combination or the other is a group, this group is a more additional indication while using in each case only four ternary values, this is further indication VT for example a registration indication transmitted together time as the first data message or DB information data to be transmitted. Ainsi par ex emple si les diff rentes donn es ternaires sont consid r es comme susceptibles de prendre les valeurs , - et 0 on aura par exemple les deux combinaisons - - et - - 0 - pour traduire le groupement binaire 0100 suivant qu il est ou non affect d une indication suppl mentaire For example, if the different ternary data is considered likely to take the values , - and 0 we have for example the two combinations - - and - - 0 - to translate the binary group 0100 according to whether or not assigned an additional indication. Dans une variante de r alisation o les donn es ternaires sont destin es tre transmises sur une liaison relativement longue par l interm diaire de transformateurs on s efforce d liminer les combi - naisons de quatre valeurs ternaires qui sont les plus susceptibles de g n rer une composante continue, ce qui conduit s lectionner les combinaisons en fonction de leur poids, celles de poids le plus faible tant pr f rable In an alternative embodiment where the ternary data is to be transmitted over a relatively long link via transformers efforts are made to eliminate com - binations of four ternary values that are most likely to generate a DC component which leads to select the combinations according to their weight, those of lowest weight being preferable. Dans la variante voqu e ci-dessus, on s lectionne aussi seize des dix-neuf combinaisons ternaires de poids nul, telle la combinaison - - , pour l un des deux ensembles de seize combinaisons qui correspondent aux seize groupements de quatre valeurs binaires non associ es des indications suppl mentaires dans la mesure o il correspond l ensemble le plus employ que l on appelle C1 In the variant described above, is selected as sixteen nineteen zero weight ternary combinations such as the combination - - for one of the two sets of sixteen combinations which correspond to the sixteen groups of four binary values not associated with additional guidance in so far as it corresponds to all the most widely used is called C1.On s lectionne aussi huit combinaisons de poids 1 et huit combinaisons de poids - 1 pour le second ensemble C2 de seize combinaisons correspondant aux seize groupements de quatre valeurs binaires qui sont associ s chacun une indication suppl mentaire, par exemple les combinaisons - 0 - de poids - 1, et 0 - de poids 1 Toutes les autres combinaisons sont consid r es comme anormales et d finissent un ensemble CX It also selects eight combinations of weight 1 and eight combinations of weight - 1 to the second set of sixteen combinations C2 corresponding to sixteen groups of four binary values which are each associated with an additional indication, such combinations - 0 - of Weight - 1 and 0 - weight 1 All other combinations are considered abnormal and define a set CX. De plus dans la mesure o l on d sire profiter des transitions entre donn es ternaires pour reconstituer les signaux d horloge H d mission de donn es la r ception on s efforce d viter les combinaisons conduisant seules ou e n combinaison des suites de z ro, telles les combinaisons ternaires 0 0 0 0 ou 0 0 0 et 0 0 0 ou encore - 0 0 0 et 0 0 0 - In addition to the extent it is desired to take advantage of the transitions between the ternary data to reconstruct the clock H for transmitting data signals to the reception attempt is made d viter combinations leading alone or in combination to zero suites ternary combinations such as 0 0 0 0 or 0 0 0 0 0 0 or - 0 0 0 0 0 0.On vite les combinaisons conduisant de trop longues impulsions, sans transition de par leurs ventuelles combinaisons, telles - - et - - Avoids the combinations leading to too long pulses without transition by their possible combinations, such - - and. On peut galement choisir selon une autre variante de r alisation des combinaisons pour l ensemble C2 qui soient tr s diff rentes des combinaisons C1 par leur organisation One can also choose according to another alternative embodiment combinations for all C2 that are very different combinations C 1 by their organization. Ainsi dans le cas de liaisons relativement courtes, par exemple de moins de cinquante m tres pour lesquelles on veut un rep rage rapide en cas de d faillance on choisit au contraire des combinaisons de l ensemble C2 ayant un poids lev de deux ou trois qui ne peuvent tre imit es par les l ments ternaires composant les combinaisons de l ensemble C1 Thus in the case of relatively short connections, for example less than fifty meters for which it is desired for quick retrieval in case of failure is selected in contrast to the combinations of all C2 having a high weight of two or three may be imitated by the ternary component elements of the combinations of all C1.En fonctionnement normal on transmet donc une succession de combinaisons appartenant l ensemble C1 entre lesquelles sont individuellement et r guli rement ins r es des combinaisons appartenant l ensemble C2 chaque combinaison C2 tant normalement s par e de tout autre combinaison C2 par une suite de combinai sons C1 In normal operation it therefore transmits a succession of combinations from the set C1, between which are inserted individually and regularly combinations belonging to the set C2, C2 each combination being normally separated from any other combination C2 by a series combination of C1.Dans les diff rentes variantes on s efforce g n ralement d viter au maximum les ventuelles imitations de combinaisons C2 par la suite des donn es ternaires constituant les combinaisons C1 au moins pendant les p riodes o les confusions sont perturbatrices, notamment lorsque l apparition d une combinaison C2 est pr visible ou pr vue In the different variants is generally seeks to avoid as much as possible combinations imitations C2 later ternary data constituting the combinations C1 at least during periods of confusion are disturbing, especially when the occurrence of a combination C2 is predictable or expected. En ce but en premier lieu on tient compte des ventuelles r currences pr vues pour les com binaisons C2, soit que par exemple l on ait affaire une r currence cyclique comme celle obtenue lorsque les indications suppl mentaires sont des indications de verrouillage de trame, ou une r currence acyclique fixe comme dans le cas de messages de longueur pr d termin e In this aim we first consider any recurrences provided for C2 combinations or as for example one is dealing with a cyclical recurrence as that obtained when the additional indications are framing indications or recurrence acyclic fixed as in the case of predetermined length messages Un simple comptage permet alors de v rifier si il y a bien transmission d une combinaison C2 l instant pr vu et de d clencher une recherche en l absence d une telle combinaison un tel instant A simple count is then used to check whether there has transmission of a combination C2 at the scheduled time and triggering a search in the absence of such a combination for such a moment. En second lieu comme on l a vu pour au moins certains cas o la confusion peut ais ment tre vit e, on emp che les imitations des combinaisons C2 par les donn es ternaires constituant les combinaisons Cl qui les entourent en s arrangeant pour que ces donn es ternaires ne puissent constituer que des combinaisons ternaires C1 ou anormales c est - - dire non pr vues parmi les trente deux combinaisons retenues Secondly as we have seen at least some cases where confusion can easily be avoided, are prevented by imitations combinations C2 ternary data constituting Cl combinations around them by arranging for these ternary data may constitute as ternary combinations C1 or abnormal is to say not provided among the thirty-two combinations retained. En effet, si l on a par exemple la succession de deux combinaisons Cl telles que - -, - 0 0 il est clair que la prise en compte des quatre donn es ternaires m dianes -, - 0 correspond une combinaison de poids - 1, qui peut correspondre soit une combinaison anormale, soit une combinaison C2, suivant les choix effectu s Indeed, if the two Cl combinations succession was such as - - - 0 0 it is clear that the inclusion of the four middle ternary data - - 0 is a combination of weight - 1, which may correspond to either an abnormal combination, or a combination of C2, following the choices made Ceci n tant g nant qu partir du moment o le rep rage des combinaisons est perdu ou incertain This being annoying that from the time the identification of combinations is lost or uncertain L indication suppl mentaire fournie par cette ventuelle fausse combinaison C2 est bien entendu elle aussi erronn e, par exemple lorsqu elle signale tort un verrouillage de trame The additional indication provided by this false possible combination C2 is of course also erroneous, for example when it incorrectly reports a frame alignment. Dans la mesure o on ne peut totalement viter les risques de confusion et o en particulier la suite des combinaisons tablies partir des informations binaires DB transmettre n est pas pr visible au n iveau de la liaison de transmission 2, on r serve les possibilit s existantes certaines combinaisons d int r t commun, par exemple la mise sous tension en cas d informations de vide, de perte de verrouillage en amont de la liaison, ou en cas de verrouillage de trame MIC To the extent that we can completely avoid confusion and where especially following combinations derived from binary data to transmit DB is not foreseeable at the transmission link 2, opportunities were provided to some combinations of common interest, such as powering when empty information, upstream locking loss of the link, or in the case of PCM frame alignment. On s arrange par exemple pour que les combinaisons ternaires C1 choisies pour les informations de vide, de perte d verrouillage ou de verrouillage de trame MIC ne puissent avoir des configurations de donn es ternaires pouvant imiter une combinaison C2 It is arranged such that the ternary C1 combinations selected for the vacuum information, blocking or frame lo cking loss MIC can not have ternary data pattern may emulate a combination C2.Ainsi dans le cas d une succession d informations binaires DB vides, qui sont classiquement g n r es sous forme d une succession de donn es binaires de valeurs altern es par les codecs MIC on choisit de transcoder chaque groupement de donn es binaires 0 1 0 1 par une combinaison ternaire C1 gale 0 0 - donnant donc naissance une suite 0 0 - 0 0 - 0 0 - qui conduit des quartets de poids nul correspondants soit une combinaison C1 juste 0 0 - soit une combinaison C1 erronn e ou non pr vue telles 0 - 0, - 0 0 ou - 0 0 si la premi re donn e prise en compte pour un quartet est la seconde, la troisi me ou la quatri me de la suite Thus in the case of a succession of binary information DB voids, which are typically generated as a binary data sequence of alternating values by the PCM codec is selected to transcode each binary data 0 1 0 1 group by a ternary combination C1 equals 0 0 - so giving rise to a sequence 0 0 - 0 0 - 0 0 - which leads to corresponding zero weight quartets is a fair combination C1 0 0 - or a combination C1 erroneous or not provided such 0 - 0 - 0 0 or - 0 0 if the first given consideration for a nibble is the second, third or fourth of the suite Ceci sans que jamais l un des d calages ne puissent jamais correspondre une combinaison C2 qui est n cessairement de poids unit affect d un signe positif ou n gatif This without ever one of the offsets can never match a combination that is necessarily C2 unit weight assigned a positive or negative sign. Il en est de m me dans le cas d une succession d informations indiquant une perte de verrouillage en amont de la liaison par une succession de valeurs binaires unit qui est traduite par la combinaison ternaire C1 gale 0 0 - donnant naissance une suite 0 0 - 0 0 - qui ne comprend que des combinaisons C1 de poids nul quel que soit la donn e ternaire prise comme premi re donn e pour une combinaison de quatre donn es successives, et qui ne p eut donc pas donner naissance une combinaison C2 de poids unit It is the same in the case of a succession of information indicating an upstream loss of lock of the connection by a sequence of binary values which unit is translated by the ternary combination C1 equal to 0 0 - giving rise to a Following 0 0-0 0 - which includes only C1 combinations zero weight regardless of the ternary data taken as primary for a combination of four successive data and therefore can not give birth C2 to a combination of weight unit. De m me dans le cas d un verrouillage de trame MIC classique les deux combinaisons ternaires successives correspondant un tel verrouillage sont - 0 0 0 - 0 qui donnent naissance des combinaisons C1 erronn es - 0 0 ou 0 0 -, 0 0 -, mais pas une combinaison C2 Similarly in the case of a conventional PCM frame locking the two successive ternary combinations corresponding to such a locking is - 0 0 0-0 which give rise to erroneous combinations C1 - 0 0 or 0 0 -, 0 0 - but not a co mbination C2.A titre d exemple un jeu de combinaisons retenues est ici pr sent dans le tableau ci-dessous comportant seize groupements de quatre valeurs binaires r f renc s 0 9 et A F et les deux combinaisons ternaires C1 et C2 qui correspondent chaque groupement For example a set of selected combinations is here presented in the table below with sixteen groups of four binary values referenced 0 to 9 and A to F and the two ternary combinations C1 and C2 corresponding to each group. Un tel code pr sente l avantage d tre bien adapt la transmission sur des liaisons relativement longues en raison des combinaisons retenues qui conduisent une composante continue n gligeable This code has the advantage of being suitable for transmission over relatively long routes due to withholding combinations that lead to a significant DC component. Quelque soit le choix, le dispositif codeur destin produire ces combinaisons a pour avantage important sa simplicit ainsi que le montre la suite de la descriptio n Whatever the choice, the encoder device for producing these combinations has the significant advantage of its simplicity and shown in the description below. Ce dispositif codeur est constitu comme il a t dit plus haut par un transcodeur binaire-binaire 6 et un convertisseur binaire-ternaire 7 ins r s en s rie entre les sources d informations binaires Db et de signalisation Si et l enroulement primaire 13 du transformateur d entr e 4 de la liaison 2 The encoder device is constituted as stated above by a binary-binary transcoder 6 and a binary-ternary converter 7 inserted in series between the sources of binary Db and signaling information and if the primary winding 13 of the transformer entry 4 of the link 2.Le transcodeur 6 comporte essentiellement une m moire lecture seule 14 qui contient diff rentes associations de donn es binaires permettant de convertir chacun des seize groupements possibles de quatre valeurs binaires en l une o l autre de deux combinaisons ternaires The transcode r 6 essentially comprises a read only memory 14 which contains different combinations of binary data for converting each of the sixteen possible groups of four binary values in one or the other of two ternary combinations. La production de signaux ternaires , -, 0 au niveau de l enroulement primaire 13 s obtient de mani re simple par mission d une impulsion soit au niveau de l une des deux bornes d extr mit s A et B de l enroulement primaire soit au niveau de l autre pour les signaux et - et par une absence d mission pour le signal 0, tant entendu que cette mission est rythm e par l horloge H de l organe desservi par le dispositif codeur 1 alimentant l enroulement primaire 13 The production of ternary signals , -, 0 at the primary winding 13 is obtained in a simple manner by transmission of a pulse or at the level of one of the two end terminals A and B of the winding primary or at the other for signals and - and by a transmission failure for the signal 0, it being understood that this program is paced by clock H organ served by the encoder device 1 drives the primary winding 13.En ce but le convertisseur 7 comporte deux registres d calage 15 et 16 identiques, de type parall le-s rie, ayant chacun leur sortie s rie reli e l une des bornes A et B de l enroulement 13 via un agencement de mise en forme d impulsion ici symbolis par un montage amplificateur 17 ou 18 In this purpose the converter 7 comprises two shift registers 15 and 16 identical, parallel-serial type, each having its serial output connected to one of the terminals A and B of the coil 13 via a shaping arrangement of pulse here symbolized by an amplifier circuit 17 or 18.Les registres d calage 15 et 16 sont synchronis s par l horloge d mission H, ils sont pr vus pour contenir chacun une succession de bits un ou z ro conduisant respectivement l mission ou non d une impulsion sur la borne que chacun dessert pendant un temps d horloge d mission H, fourni l entr e de lecture R de chacun des registres Shift reg isters 15 and 16 are synchronized by the transmission clock H, they are intended to contain each a succession of bits one or zero, respectively, leading to the issue or not a pulse on terminal each for dessert H transmit clock time provided to the read input R of each of the registers. En ce but, la m moire lecture seule 14 fournit tous les quatre temps d horloge quatre donn es binaires chacun des registres 15 et 16 contr l s en ce but via leur entr e d criture W In this purpose, the read only memory 14 provides all four clock time four binary data to each of the registers 15 and 16 controlled in this order via their write input W. Dans une forme pr f r e de r alisation chaque groupement de quatre donn es binaires adresse l une ou l autre de deux associations de huit donn es binaires en m moire lecture seule 14, suivant la pr sence ou non d une indication suppl mentaire mettre In a preferred embodiment, each group of four binary data address one or the other of two groups of eight binary data in read only memory 14, as the presence or absence of an additional indication to be transmitted Les huit donn es binaires d une association sont scind es en deux groupes de quatre donn es et ces groupes sont simultan ment transmis en parall le aux deux registres 15 et 16 aux fins d mission The eight bit data of an association are divided into two groups of four data and these groups are simultaneously transmitted in parallel to the two registers 15 and 16 for issuance. Pour cela, la m moire lecture seule 14 contient trente-deux associations individuellement adressables de huit donn es binaires, ces trente deux associations sont r parties en deux groupes de seize et chaque groupe correspond l un des deux ensembles de seize combinaisons ternaires C1 ou C2 For this, the read only memory 14 contains thirty-two individually addressable associations of eight binary data, these thirty two associations are divided into two groups of sixteen and each group corresponds to one of the two se ts of sixteen ternary combinations C1 or C2.L adressage en lecture de la m moire lecture seule 14 s effectue l aide d un signal d horloge H 4 obtenu partir du signal H et du signal d indication suppl mentaire VT qui s lectionne l un o l autre des deux groupes de seize associations suivant sa pr sence ou son absence, l adressage de chaque association dans son groupe s effectuant partir d un des seize groupements de quatre donn es binaires The read addressing the read only memory 14 is carried out using a clock signal H 4 derived from the H signal and the further indication signal VT which selects one where the other two groups of sixteen groups according to the presence or absence, the addressing of each association as a performing group from one of sixteen groups of four binary data En ce but, les informations binaires DB et la signalisation SI sont fournis quartet par quartet aux entr es d adressage de la m moire lecture seule 14 en parall le avec l indication suppl mentaire VT de man i re former un quintet d adressage, tant entendu que les informations binaires DB et la signalisation SI sont mutuellement exclusives ainsi que le symbolise une porte 19 de type OU exclusif pr sent e figure 2 et que la m moire lecture seule 14 est lue tous les quatre temps d horloge d mission signal H 4 In this purpose, the binary information DB and the IF signal are provided nibble by nibble to read the memory address inputs only 14 in parallel with the additional indication VT to form an addressing quintet, it being understood that binary information DB and SI signaling are mutually exclusive and the type symbolizes an exclusive OR gate 19 shown in Figure 2 and the read-only memory 14 is played every four beats of transmit clock signal H 4.Le dispositif d codeur 2 figure 3 est galement de constitution simple, il comporte deux classiques circuits 21, 22 de mise en forme des signaux re us qui sont plac s aux bornes du secondaire 20 du transformateur de sortie 5 Ces circuits de mise en forme 21, 22 alimentent le circuit de reconstitution d horloge 9 qui met classiquement profit les transitions des signaux en sortie des circuits de mise en forme pour fournir un signal d horloge reconstitu reproduisant les signaux d horloge H ayant pr sid l mission par le dispositif codeur 1 ainsi qu indiqu plus haut The decoder device 2 Figure 3 is also simple constitution, it has two conventional circuits 21, 22 for shaping the received signals that are placed across the secondary 20 of the output transformer 5 These shaping circuits 21, 22 supply the clock recovery circuit 9 which typically leverages the transitions at the output of shaping circuit signals to provide a recovered clock reproducing the H clock signals that governed the issue by the encoder device 1 as mentioned above. Les circuit de remise en forme 21 et 22 alimentent galement deux unit s de registres 23 et 24 du convertisseur ternaire-binaire 8 qui enregistrent chacun le niveau du signal en sortie d un circuit de mise en forme au rythme du signal d horloge reconstitu HR Fitness circuit 21 and 22 also feed two registers of units 23 and 24 of the ternary-binary converter 8 which each recorded signal level at the output of a shaping circuit at the rhythm of the recovered clock signal HR. Chaque unit de registre comporte par exemple un premier registre entr e s rie et sorties parall les 25 et 26, l entr e de chacun de ces registres est reli e en sortie d un circuit de remise en forme 21 et 22 et les sorties de chacun sont connect es aux bornes d entr e d un second registre 27 ou 28 de type entr es et sorties parall les Each register unit comprises for example a first register with parallel input and output series 25 and 26, the input of each of these registers is connected to the output of a fitness circuit 21 and 22 and all outputs are connected to the input terminals of a second register 27 or 28 of the type with parallel inputs and outputs. L criture en premiers registres 25, 26 s effectue simultan me nt au rythme de l horloge reconstitu e HR et la lecture des seconds registres 27, 28 s effectue au rythme de l horloge reconstitu HR n avec n gal au nombre de bits en parall le dans chaque registre, soit n 4 dans l exemple pr sent The write first registers 25, 26 takes place simultaneously to the rhythm of the recovered clock HR and reading the second registers 27, 28 is performed to the rhythm of the clock reconstructed HR n, where n equals the number of bits in parallel in each register or n 4 in the example. Les sorties des registres 27 et 28 sont reli es autant d entr es d un d codeur 29 assurant l adressage d une m moire lecture seule 31 dans le transcodeur binaire-binaire 11 The outputs of registers 27 and 28 are connected to as many inputs of a decoder 29 providing the addressing of a read-only memory 31 in the binary-binary transcoder 11.Cette m moire lecture seule 31 a des sorties du type trois tats et elle ne comporte que trente deux lignes correspondant aux trente deux combin aisons retenues qui sont seules susceptibles de l activer This read-only memory 31 has outputs type three states and has only thirty-two lines corresponding to thirty-two selected combinations that are only likely to activate Chaque ligne comprend un groupement de quatre donn es binaires et une indication C1 ou VT relative l ensemble de combinaisons C1 ou C2 qui a permis son adressage Each line comprises a group of four binary data, and a C1 or VT indication relating to all combinations of C1 or C2 which has its address. A chaque adressage par huit bits fournis simultan ment par les registres 27, 28 correspond donc soit la transmission parall le de quatre donn es binaires de la m moire 31 vers un registre d mission 32 si la combinaison d adressage est l une des trente deux combinaisons pr vues, soit une indication CX en sortie de d codeur 29 si la combinaison d adressage est diff rente At each address by eight bits simultaneously supplied by the registers 27, 28 thus corresponds to eith er the parallel transmission of four bit data of the memory 31 to a transmit register 32 if the address combination is one of the thirty two combinations provided or an indication CX decoder output 29 if the address combination is different. En ce but les huit bits fournis par les deux seconds registres 27, 28 tous les quatre temps d horloge HR sont appliqu s une matrice de compactage incorpor e au d codeur 31 qui en d duit une combinaison de cinq bits destin e servir l adressage des lignes de la m moire lecture seule 31 o fournir l indication CX ventuellement associ e des indications annexes non r pertori es ici In order eight bits provided by the two second registers 27, 28 all four HR clock time are applied to a compaction die incorporated in the decoder 31 which derives a combination of five bits for use in addressing the lines of the read only memory 31 which provide an indication CX possibly combined with ancillary information not listed here. Les indications C1 et VT sont fournies avec les donn es binaires D en sortie de m moire 31 et une indication d anormalit CX permet de signaler toute combinaison d adressage anormale, c est - - dire non comprise dans les trente-deux combinaisons pr vues C1 and VT indications are provided with binary data D memory output 31 and an indication of abnormality CX used to report any combination of abnormal addressing, that is to say, not included in the thirty-two combinations provided. L indication VT est fournie un automate contr leur 33 du circuit de contr le 10, elle est combin e avec une information de verrouillage interne TO fournie par un compteur-d compteur 34 qui re oit une indication du circuit de reconstitution d horloge 9 tous les m temps d horloge m tant choisi gal quatre dans l exemple choisi ou la trame comporte quatre voies et o il y a un verrouillage de trame toutes les quatre voies The VT indication is provided to a controller 33 of the controller control circuit 10, it is combined with an internal locking informat ion TO provided by a down counter 34 which receives an indication of the clock recovery circuit 9 every m clock time m is set equal to four in the example chosen or the frame comprises four channels and wherein there is a frame locking all four channels. L automate contr leur 33 dont le fonctionnement est voqu ci-dessous fournit un signal de pr positionnement au d compteur 34, un signal de verrouillage r cup r VR pour le registre d mission 32 qui alimente en donn es re ues l organe desservi par le dispositif d codeur 3 ici consid r et un signal de contr le X de la commande de lecture HR 4 des seconds registres 27, 28 tous les quatre temps d horloge HR en liaison avec le circuit de r cup ration d horloge 9 The PLC controller 33 whose operation is discussed below provides a preset signal to the down counter 34, a recovered latch signal VR to the transmit register 32 that supplies data received organ served by the decoding device 3 here considered and a control signal X from the read contr ol HR 4 second registers 27, 28 all four RH clock time in association with the clock recovery circuit 9.Le signal CX est utilis pour modifier le temps de lecture des registres 27 et 28 en cas de mauvais calage The CX signal is used to change the playing time of the registers 27 and 28 in case of bad timing. En ce but le signal CX est transmis l automate contr leur 33 qui, par le signal de contr le X, est apte d caler le signal HR 4 de commande de lecture d un nombre pr d termin de temps d horloge HR par exemple trois de mani re tenter de retrouver l indication de verrouillage C2 perdue In this purpose the signal CX is transmitted to the PLC controller 33, which, by the X-control signal is adapted to shift the signal HR 4 read command a predetermined number of clock times HR for example three so try to find the indication of C2 lost lock. Les diff rentes op rations r alis es par le dispositif d codeur 3 et les diff rents tats atteints sont symbolis s par le diagramme pr sent figure 4 pour un syst me dans lequel c est une indication de verrouillage de trame temporelle qui constitue l indication suppl mentaire VT transmise par codage des quartets au moyen des combinaisons choisies dans l ensemble C2 The various operations performed by the decoding device 3 and with different states are symbolized by the diagram shown in FIG 4 for a system in which this is a temporal framing indication that constitutes the additional VT indication transmitted by encoding the nibbles means combinations selected from the group C2.La premi re op ration n cessaire au fonctionnement du dispositif d codeur 3 en d but de transmission est la recherche de verrouillage correspondant un tat r f renc 0 sur la figure 4, elle doit permettre de d coder convenablement les donn es re ues ult rieurement The first operation necessary to the operation of the decoder device 3 at the start of transmission is the locking mark corresponding to a reference state 0 in Figure 4, it is possible to properly decode th e data received later. L l ment d terminant est la r ception d une combinaison de l ensemble C2 par le transcodeur 11 via les registres 23 et 24 The determining factor is receiving a combination of all C2 by the transcoder 11 via the registers 23 and 24.A la mise en marche de la liaison une telle combinaison C2 est g n ralement utilis e pour le premier quartet mis et permet donc de synchroniser imm diatement le d codeur 3, elle se traduit par l apparition d un signal VT en sortie de m moire lecture seule 31 A setting such a combination C2 running of the link is generally used for the first quartet issued and therefore synchronizes immediately decoder 3, it results in the appearance of a VT signal in read only memory output 31.Le transcodeur 11 assure alors le pr positionnement du d compteur 34 sa position initiale pour le comptage d un temps gal la dur e d une trame la fin duquel ce d compteur mettra un signal de verrouillage interne TO, le pr positionnement est assur par un signal PR d e l automate de contr le 33 The transcoder 11 then performs the presetting of the down counter 34 to its initial position for counting a time equal to the duration of a frame at the end of which the down counter will issue an internal lock signal TO, the pre-positioning is ensured by a signal PR of the supervisory controller 33.Ceci occasionne le passage du dispositif d codeur 3 de l tat de recherche un tat de prise r f renc 1 sur la figure 4 pour lequel toute transmission des donn es re ues vers l organe r cepteur est bloqu e par absence de signal VR de m me que dans l tat 0 pr c dent This causes the passage of the decoder 3 of the search device in a state engaged state referenced 1 in Figure 4 in which all of the received data transmission to the receiver is blocked by absence of signal VR as well as in the 0 precedent A partir de cet tat 1 , les l ments normalement d terminants sont la r ception d une seconde combinaison C2 de valeur identique ou diff rente, simultan ment avec un si gnal de verrouillage interne TO fourni par le d compteur 34 En ce cas r ception du signal VT l automate de contr le 33 met le signal de pr positionnement PR vers le d compteur 34 et un signal de verrouillage r cup r VR permettant la transmission des quatre valeurs binaires paraissant en parall le en sortie D de m moire 31 en vue de leur mission par le registre d mission 32 vers l organe r cepteur que dessert le dispositif d codeur 3 From this state 1 , the key elements are normally receiving a second combination of identical or different C2 value, simultaneously with an internal lock signal provided by the down counter TO 34 In this case the reception signal VT the supervisory controller 33 outputs the preset signal PR to the down counter 34 and an RV recovered lock signal allowing the transmission of four binary values appearing in parallel output D memory 31 for their issuance by the transmit register 32 toward the receiver served by the decoder device 3.L tat atteint est alors un ta t de synchronisme r f renc 2 sur la figure 4 The state is then reached a synchronism condition referenced 2 in Figure 4.Un autre l ment d terminant partir de l tat 1 est la r ception d une combinaison C2 pr alablement l coulement d une trame depuis la pr c dente combinaison C2, c est - - dire avant r ception d un verrouillage de trame interne TO Another determining factor from the 1 state is receiving a combination C2 prior to the lapse of a frame from the previous combination C2, that is to say, before receiving a locking Internal frame TO. Ceci indique que l une des deux combinaisons C2 successivement re ues est imit e et l on consid re arbitrairement que la derni re combinaison re ue est la bonne en repositionnant le d compteur 34 en position initiale par l interm diaire du signal PR et r ception du signal VT, en revenant l tat de prise 1 , pour la suite de la proc dure This indicates that one of the two combinations C2 successively received is imitated and is arbitrarily considered th at the latter combination is received the proper repositioning the down counter 34 to the initial position via the RA signal and receipt of signal VT, by returning to the decision 1 for the rest of the procedure. Un l ment d terminant suppl mentaire partir de l tat 1 est la r ception d un verrouillage de trame interne TO avant r ception d une autre combinaison C2 An additional key element from the state 1 is receiving an internal framing TO before receiving another combination C2 Ceci conduit un retour l tat initial de recherche r f renc 0 dans la mesure o la combinaison C2 ayant pr alablement conduit l tat 1 tait probablement une imitation due un mauvais calage This leads to a return to the initial state referenced research 0 to the extent that the combination C2 having previously led to the 1 was probably an imitation due to bad timing. L apparition d une combinaison de l ensemble CX constitue galement un l ment d terminant partir de l tat de prise 1 dans la mesure o il traduit une fau te de transmission ou de codage que le d codeur 29 sait diff rencier, il conduit un retour l tat de recherche 0 , avec un d calage qui est par exemple de trois bits au niveau de chaque ensemble de registres 23, 24, sous le contr le du signal X The appearance of a combination of all CX is also a key element from the taking of 1 to the extent that it reflects a lack of transmission or coding the decoder 29 knows differentiate it leads a return to the state of mark 0 , with an offset which is for example of three bits in each set of registers 23, 24, under the control of the signal X. On notera galement la possibilit de mise en recherche par une information de remise z ro RZI par l organe desservi, cette possibilit ne sera pas d velopp e ici plus avant Note also the ability to search by setting reset information RZI served by the body, this opportunity will not be developed further here. Lorsque le synchronisme a t tabli tat 2 , l l ment d terminant est la r ception d un verrouillage de tra me interne TO qui d clenche la v rification d existence simultan e ou coincidence d une combinaison C2 traduite par la pr sence d un signal VT au niveau de l automate de contr le 33 When the synchronization has been established 2 , the decisive factor is the receipt of a TO-house framing that triggers the verification of simultaneous existence of a coincidence or C2 combination resulted in the presence of a VT signal at the control of controller 33.Si une telle coincidence existe il y a mission d un signal de verrouillage r cup r VR vers le registre d mission pour valider l mission et un nouveau signal PR de repositionnement l tat initial de comptage du d compteur 26 L automate reste l tat synchronis 2 If such a coincidence is there issue a recovered latch signal VR to the transmit register and to validate the emission of a new reset signal PR to the initial counting state of the down counter 26 The controller remains the synchronized state 2.Si la coincidence ne se produit pas, il y a mission des signaux VR et PR, l automate passe un tat de contr le 3 dans lequel il attend normalement la r ception d un second verrouillage de trame interne TO pour v rifier une nouvelle fois la coincidence avec une combinaison C2 If the coincidence does not occur, there issuance of VR and PR signals, the controller goes to a control state 3 in which he usually waits to receive a second TO internal framing to check new time coincidence with a combination C2 Si cette co ncidence se produit l automate revient dans son tat synchronis 2 et met les signaux VR et PR, au cas contraire l automate repasse son tat initial de recherche de synchronisation 0 If this coincidence occurs the controller returns to its synchronized state 2 and outputs the RV and PR signals, otherwise the controller will return to its original state research synchronization 0.